18
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 11. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost Empty
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 10.
FFBFFB
FFBFFB
FFB
Flag Timing and First Available Write when FIFO2 is Full
CSA
EFA
MBA
ENA
A0 - A35
CLKA
FFB
CLKB
CSB
4659 drw 13
W/RB
12
B0 - B35
MBB
ENB
tCLK
tCLKH tCLKL
tENS2 tENH2
tA
tSKEW1
tCLK
tCLKH tCLKL
tENS3
tENS2
tDS
tENH3
tENH2
tDH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO2 Full
tWFF
tWFF
AEB
CLKA
ENB
4659 drw 14
ENA
CLKB
2
1
t
ENS2
t
ENH2
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH2
X Words in FIFO1 (X+1) Words in FIFO1
(1)
