LTC3411
16
3411fb
To avoid the LTC3411 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3411 is
in dropout at an input voltage of 3.3V with a load current
of 1A. From the Typical Performance Characteristics
graph of Switch Resistance, the R
DS(ON)
resistance of the
P-channel switch is 0.11Ω. Therefore, power dissipated
by the part is:
P
D
= I
2
• R
DS(ON)
= 110mW
The MS10 package junction-to-ambient thermal resistance,
θ
JA
, will be in the range of 100°C/W to 120°C/W. Therefore,
the junction temperature of the regulator operating in a
70°C ambient temperature is approximately:
T
J
= 0.11 • 120 + 70 = 83.2°C
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 25°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
APPLICATIONS INFORMATION
Design Example
As a design example, consider using the LTC3411 in a por-
table application with a Li-Ion battery. The battery provides
a V
IN
= 2.5V to 4.2V. The load requires a maximum of 1A
in active mode and 10mA in standby mode. The output
voltage is V
OUT
= 2.5V. Since the load still needs power in
standby, Burst Mode operation is selected for good low
load effi ciency.
First, calculate the timing resistor:
R MHz k
T
=
()
=
9 78 10 1 323 8
11
108
.• .
.
Use a standard value of 324k. Next, calculate the inductor
value with 40% ripple current which is 500mA
:
L
V
MHz mA
V
V
H=−
25
1 500
1
25
42
2
.
.
.
Choosing the closest inductor from a vendor of 2.2μH,
results in a maximum ripple current of:
Δ=
μ
=I
V
MHz
V
V
mA
L
25
122
1
25
42
460
.
•.
.
.
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C
A
MHz V
F
OUT
≈=μ25
1
1525
20.
•( % . )
The closest standard value is 22μF. Since the output
impedance of a Li-Ion battery is very low, C
IN
is typically
10μF. In noisy environments, decoupling SV
IN
from PV
IN
with an R6/C8 fi lter of 1Ω/0.1μF may help, but is typically
not needed.
LTC3411
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APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high effi ciency, the
current in these resistors should be kept small. Choosing
2μA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3411 is with a 13kΩ and 1000pF fi lter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.
Figure 1 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3411. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 6)
and power GND (Pin 5) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to PGND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line terminated
near SGND (Pin 3). The feedback signal V
FB
should be
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C
IN
, the compensation capacitor C
C
and
C
ITH
and all the resistors R1, R2, R
T
, and R
C
should be
routed away from the SW trace and the inductor L1.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PV
IN
, PGND, SV
IN
or SGND.
PV
IN
LTC3411
PGND
SW
SV
IN
SGND
PGOODPGOOD
V
FB
SYNC/MODE
I
TH
SHDN/R
T
L1
V
IN
BMPS
V
IN
V
OUT
R5
R
T
R3R1R2
3411 F06
C3
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
C
OUT
C4
Figure 6. LTC3411 Layout Diagram (See Board Layout Checklist)
LTC3411
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TYPICAL APPLICATIONS
SV
IN
LTC3411
PGOOD PGOOD
SW
PV
IN
SYNC/MODE V
FB
I
TH
SHDN/R
T
SGND
L1
2.2μH
V
IN
2.63V TO
5.5V
V
OUT
1.8V/2.5V/3.3V
AT 1.25A
R5
100k
R4
324k
R1A
280k
R3
13k
RS1
1M
BM
RS2
1M
3411 F07a
C3
1000pF
C4 22pF
R2 887K
C2
22μF
SGND SGND
R1B
412k
R1C
698k
PS
FC
PGND
C1
22μF
PGND
PGNDSGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
GND
3.3V 2.5V 1.8V
Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors
LOAD CURRENT (mA)
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
1 100 1000 10000
3411 F07b
10
PULSE SKIP
(PS)
FORCED
CONTINUOUS (FC)
V
IN
= 3.3V
V
OUT
= 2.5V
f
O
= 1MHz
Burst Mode
OPERATION (BM)
Effi ciency vs Load Current

LTC3411EDD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.25A, 4MHz, Sync Buck DC/DC Conv
Lifecycle:
New from this manufacturer.
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