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74HCT193N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 13 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8. Dynamic characteristics type 74HC193
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
t
pd
propagation
delay
CPU, CPD to Qn;
see Figure 9
[1]
-
V
CC
= 2.0 V - 63 215 - 270 - 325 ns
V
CC
= 4.5 V - 23 43 - 54 - 65 ns
V
CC
= 6.0 V - 18 37 - 46 - 55 ns
CPU to TCU
; see
Figure 10
V
CC
= 2.0 V - 39 125 - 155 - 190 ns
V
CC
= 4.5 V - 14 25 - 31 - 38 ns
V
CC
= 6.0 V - 11 21 - 26 - 32 ns
CPD to TCD
; see
Figure 10
V
CC
= 2.0 V - 39 125 - 155 - 190 ns
V
CC
= 4.5 V - 14 25 - 31 - 38 ns
V
CC
= 6.0 V - 11 21 - 26 - 32 ns
PL
to Qn; see
Figure 11
V
CC
= 2.0 V - 69 220 - 275 - 330 ns
V
CC
= 4.5 V - 25 44 - 55 - 66 ns
V
CC
= 6.0 V - 20 37 - 47 - 56 ns
MR to Qn; see
Figure 12
V
CC
= 2.0 V - 58 200 - 250 - 300 ns
V
CC
= 4.5 V - 21 40 - 50 - 60 ns
V
CC
= 6.0 V - 17 34 43 - 51 ns
Dn to Qn; see
Figure 11
V
CC
= 2.0 V - 69 210 - 265 - 315 ns
V
CC
= 4.5 V - 25 42 - 53 - 63 ns
V
CC
= 6.0 V - 20 36 - 45 - 54 ns
PL
to TCU,PLto
TCD
; see Figure 14
V
CC
= 2.0 V - 80 290 - 365 - 435 ns
V
CC
= 4.5 V - 29 58 - 73 - 87 ns
V
CC
= 6.0 V - 23 49 - 62 - 74 ns
MR to TCU
,MRto
TCD; see Figure 14
V
CC
= 2.0 V - 74 285 - 355 - 430 ns
V
CC
= 4.5 V - 27 57 - 71 - 86 ns
V
CC
= 6.0 V - 22 48 - 60 - 73 ns
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 14 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
t
pd
propagation
delay
Dn to TCU,Dnto
TCD
; see Figure 14
V
CC
= 2.0 V - 80 290 - 365 - 435 ns
V
CC
= 4.5 V - 29 58 - 73 - 87 ns
V
CC
= 6.0 V - 23 49 - 62 - 74 ns
t
THL
HIGH to LOW
output transition
time
see Figure 12
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
=4.5V - 7 15 - 19 - 22 ns
V
CC
=6.0V - 6 13 - 16 - 19 ns
t
TLH
LOW to HIGH
output transition
time
see Figure 12
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
=4.5V - 7 15 - 19 - 22 ns
V
CC
=6.0V - 6 13 - 16 - 19 ns
t
W
pulse width CPU, CPD (HIGH
or LOW); see
Figure 9
V
CC
= 2.0 V 100 22 - 125 - 150 - ns
V
CC
=4.5V 20 8 - 25 - 30 - ns
V
CC
=6.0V 17 6 - 21 - 26 - ns
MR (HIGH); see
Figure 12
V
CC
= 2.0 V 100 25 - 125 - 150 - ns
V
CC
=4.5V 20 9 - 25 - 30 - ns
V
CC
=6.0V 17 7 - 21 - 26 - ns
PL
(LOW); see
Figure 11
V
CC
= 2.0 V 100 19 - 125 - 150 - ns
V
CC
=4.5V 20 7 - 25 - 30 - ns
V
CC
=6.0V 17 6 - 21 - 26 - ns
t
rec
recovery time PL to CPU, CPD;
see Figure 11
V
CC
=2.0V 50 8 - 65 - 75 - ns
V
CC
=4.5V 10 3 - 13 - 15 - ns
V
CC
=6.0V 9 2 - 11 - 13 - ns
MR to CPU, CPD;
see Figure 12
V
CC
=2.0V 50 0 - 65 - 75 - ns
V
CC
=4.5V 10 0 - 13 - 15 - ns
V
CC
=6.0V 9 0 - 11 - 13 - ns
Table 8. Dynamic characteristics type 74HC193
…continued
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 15 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
t
su
set-up time Dn to PL; see
Figure 13
; note:
CPU = CPD =
HIGH
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
=4.5V 16 8 - 20 - 24 - ns
V
CC
=6.0V 14 6 - 17 - 20 - ns
t
h
hold time Dn to PL; see
Figure 13
V
CC
=2.0V 0 14 - 0 - 0 - ns
V
CC
=4.5V 0 5- 0 - 0 -ns
V
CC
=6.0V 0 4- 0 0 -ns
CPU to CPD,
CPD to CPU; see
Figure 15
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
=4.5V 16 8 - 20 - 24 - ns
V
CC
=6.0V 8 6 - 17 - 20 - ns
f
max
maximum
frequency
CPU, CPD; see
Figure 9
V
CC
= 2.0 V 4.0 13.5 - 3.2 - 2.6 - MHz
V
CC
=4.5V 20 41 - 16 - 13 - MHz
V
CC
=6.0V 24 49 - 19 - 15 - MHz
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC
;
V
CC
=5V;
f
i
=1MHz
[2]
-24- - - - -pF
Table 8. Dynamic characteristics type 74HC193
…continued
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

74HCT193N,652

Mfr. #:
Buy 74HCT193N,652
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 4-BIT BINARY UP/DOWN
Lifecycle:
New from this manufacturer.
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