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74HCT193N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
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74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 4 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Fig 4. Logic diagram
001aag412
D0 D1 D2 D3
Q0 Q1 Q2 Q3
TCD
PL
CPU
CPD
MR
SD
FF1
RD
Q
Q
T
SD
FF2
RD
Q
Q
T
SD
FF3
RD
Q
Q
T
SD
FF4
RD
Q
Q
T
TCU
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 5 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] LOW-to-HIGH, edge triggered.
Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16
and SSOP16
Fig 7. Pin configuration DIP16
D1
V
CC
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
GND D3
001aag406
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC193
74HCT193
74HC193
74HCT193
D1 V
CC
Q1 D0
Q0 MR
CPD TCD
CPU TCU
Q2 PL
Q3 D2
GND D3
001aaf408
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
D0 15 data input 0
D1 1 data input 1
D2 10 data input 2
D3 9 data input 3
Q0 3 flip-flop output 0
Q1 2 flip-flop output 1
Q2 6 flip-flop output 2
Q3 7 flip-flop output 3
CPD 4 count down clock input
[1]
CPU 5 count up clock input
[1]
GND 8 ground (0 V)
PL
11 asynchronous parallel load input (active LOW)
TCU
12 terminal count up (carry) output (active LOW)
TCD
13 terminal count down (borrow) output (active LOW)
MR 14 asynchronous master reset input (active HIGH)
V
CC
16 supply voltage
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 6 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH clock transition.
[2] TC
U = CPU at terminal count up (HHHH)
[3] TC
D = CPD at terminal count down (LLLL).
Table 3. Function table
[1]
Operating mode Inputs Outputs
MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD
Reset (clear) HXXLXXXXLLLLHL
HXXHXXXXLLLLHH
Parallel load LLXLLLLLLLLLHL
LLXHLLLLLLLLHH
LLLXHHHHHHHHLH
LLHXHHHHHHHHHH
Count up L H H X X X X count up H
[2]
H
Count down L H H X X X X count down H H
[3]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

74HCT193N,652

Mfr. #:
Buy 74HCT193N,652
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 4-BIT BINARY UP/DOWN
Lifecycle:
New from this manufacturer.
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