74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 16 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Table 9. Dynamic characteristics type 74HCT193
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
t
pd
propagation
delay
CPU, CPD to Qn;
see Figure 9
[1]
V
CC
= 4.5 V - 23 43 - 54 - 65 ns
CPU to TCU
; see
Figure 10
V
CC
= 4.5 V - 15 27 - 34 - 41 ns
CPD to TCD
; see
Figure 10
V
CC
= 4.5 V - 15 27 - 34 - 41 ns
PL
to Qn; see
Figure 11
V
CC
= 4.5 V - 26 46 - 58 - 69 ns
MR to Qn; see
Figure 12
V
CC
= 4.5 V - 22 40 - 50 - 60 ns
Dn to Qn; see
Figure 11
V
CC
= 4.5 V - 27 46 - 58 - 69 ns
PL
to TCU,PLto
TCD; see Figure 14
V
CC
= 4.5 V - 31 55 - 69 - 83 ns
MR to TCU
,MRto
TCD
; see Figure 14
V
CC
= 4.5 V - 29 55 - 69 - 83 ns
Dn to TCU
,Dnto
TCD
; see Figure 14
V
CC
= 4.5 V - 32 58 - 73 - 87 ns
t
THL
HIGH to LOW
output transition
time
see Figure 12
V
CC
=4.5V - 7 15 - 19 - 22 ns
t
TLH
LOW to HIGH
output transition
time
see Figure 12
V
CC
=4.5V - 7 15 - 19 - 22 ns
t
W
pulse width CPU, CPD (HIGH
or LOW); see
Figure 9
V
CC
=4.5V 25 11 - 31 - 38 - ns
MR (HIGH); see
Figure 12
V
CC
=4.5V 20 7 - 25 - 30 - ns
PL
(LOW); see
Figure 11
V
CC
=4.5V 20 8 - 25 - 30 - ns
