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74HCT193N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 19 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
001aag415
Dn input
V
I
GND
V
I
GND
V
I
GND
V
OH
V
OL
Qn output
CPU, CPD
input
PL input V
M
V
M
V
M
V
M
t
W
t
rec
t
PLH
t
PHL
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
001aag416
MR input
Qn output
V
OH
V
OL
V
I
GND
V
I
GND
CPU, CPD
input
V
M
V
M
V
M
10 %
90 %
t
rec
t
PHL
t
THL
t
W
t
TLH
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 20 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Tabl e 1 0
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times
001aag417
Dn input
Qn output
V
OL
V
OH
GND
V
I
GND
V
I
PL input
V
M
t
su
t
h
V
M
t
su
t
h
Measurement points are given in Tabl e 1 0.
t
PLH
and t
PHL
are the same as t
pd
.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU,TCD) propagation delays
001aag418
PL, MR, Dn
input
TCU, TCD
output
t
PLH
t
PHL
V
M
V
M
V
OL
V
OH
GND
V
I
Measurement points are given in Tabl e 1 0.
Fig 15. The CPU to CPD or CPD to CPU hold times
001aag419
CPD or CPU
input
CPU or CPD
input
V
I
GND
V
I
GND
V
M
V
M
t
h
74HC_HCT193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 24 June 2013 21 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Table 10. Measurement points
Type Input Output
V
M
V
I
V
M
74HC193 0.5 V
CC
GND to V
CC
0.5 V
CC
74HCT193 1.3 V GND to 3 V 1.3 V
Test data is given in Table 11.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator
C
L
= Load capacitance including jig and probe capacitance
R
L
= Load resistor
S1 = Test selection switch
Fig 16. Load circuitry for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 11. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
74HC193 V
CC
6ns 15pF, 50 pF 1k open
74HCT193 3 V 6 ns 15 pF, 50 pF 1 k open
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

74HCT193N,652

Mfr. #:
Buy 74HCT193N,652
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 4-BIT BINARY UP/DOWN
Lifecycle:
New from this manufacturer.
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