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9DB306BLLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
PCI Express Jitter Attenuator
9DB306
Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20161
GENERAL DESCRIPTION
The 9DB306 is a high performance 1-to-6 Differential-to-
LVPECL Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found
in desktop PCs, the PCI Express clocks are generated from a
low bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a zero delay buffer may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The 9DB306
has 2 PLL bandwidth modes. In low bandwidth mode, the PLL
loop BW is about 500kHz and this setting will attenuate much of
the jitter from the reference clock input while being high enough
to pass a triangular input spread spectrum profi le. There is also
a high bandwidth mode which sets the PLL bandwidth at 1MHz
which will pass more spread spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by confi guring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC PCI
Express Applications.
FEATURES
• Six differential LVPECL output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Input frequency range: 90MHz - 140MHz
• VCO range: 450MHz - 700MHz
• Output skew: 135ps (maximum)
• Cycle-to-Cycle jitter: 30ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial temperature information available upon request
PIN ASSIGNMENT
nOE0
CLK
nCLK
BYPASS
nOE1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
BLOCK DIAGRAM
9DB306
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.925mm
body package
L Package
Top View
VEE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
V
CC
nOE0
nOE1
V
CC
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
V
EE
VCC
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PLL_BW
V
CCA
VEE
BYPASS
FS1
PCIEXT5
PCIEXC5
V
CC
9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
F Package
Top View
Phase
Detector
VCO
Loop
Filter
1 Disabled
0 Enabled
1 Disabled
0 Enabled
÷5
0 ÷4
1 ÷5
0 ÷5
1 ÷4
FS0
FS1
Internal Feedback
÷5
0
1
0
1
0
1
Buffer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20162
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Inputs Outputs
FS0 PCIEX0 PCIEX1 PCIEX2
0 1 5/4 5/4
1111
TABLE 3C. OUTPUT ENABLE
FUNCTION TABLE, nOE0
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 14, 20 V
EE
Power Negative supply pins.
2, 3
PCIEXT1,
PCIEXC1
Output Differential output pairs. LVPECL interface levels.
4, 5
PCIEXT2,
PCIEXC2
Output Differential output pairs. LVPECL interface levels.
6, 9, 15, 28 V
CC
Power Core supply pins.
7, 8 nOE0, nOE1 Input Pulldown
Output enable. When HIGH, forces true outputs (PCIEXTx) to go LOW
and the inverted outputs (PCIEXCx) to go HIGH. When LOW, outputs
are enabled. LVCMOS/LVTTL interface levels.
10, 11
PCIEXC3,
PCIEXT3
Output Differential output pairs. LVPECL interface levels.
12, 13
PCIEXC4,
PCIEXT4
Output Differential output pairs. LVPECL interface levels.
16, 17
PCIEXC5,
PCIEXT5
Output Differential output pairs. LVPECL interface levels.
18 FS1 Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
19 BYPASS Input Pulldown
Bypass select pin. When HIGH, the PLL is in bypass mode, and the
device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels.
21 V
CCA
Power Analog supply pin. Requires 24Ω series resistor.
22 PLL_BW Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
23 CLK Input Pulldown Non-inverting differential clock input.
24 nCLK Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left fl oating.
25 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
26, 27
PCIEXT0,
PCIEXC0
Output Differential output pairs. LVPECL interface levels.
NOTE:
Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs Outputs
FS1 PCIEX3 PCIEX4 PCIEX5
0111
1 5/4 5/4 5/4
Inputs Outputs
nOE0 PCIEX0:2
0 Enabled
1 Disabled
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, nOE1
Inputs Outputs
nOE1 PCIEX3:5
0 Enabled
1 Disabled
TABLE 3E. PLL BANDWIDTH
FUNCTION TABLE
Inputs
Bandwidth
PLL_BW
0 500kHz
1 1MHz
TABLE 3F. PLL MODE
FUNCTION TABLE
Inputs
PLL Mode
BYPASS
1 Disabled
0 Enabled
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20163
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
CC
= 3.3V±10%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current CLK, nCLK V
CC
= V
IN
= 3.63V 150 µA
I
IL
Input Low Current CLK, nCLK V
CC
= 3.63V, V
IN
= 0V 150 µA
V
PP
Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
+ 0.5 V
CC
- 0.85 V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 3.3V±10%, TA = 0°C TO 70°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= 3.3V±10%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 2.97 3.3 3.63 V
V
CCA
Analog Supply Voltage V
CC
– 0.60 3.3 V
CC
V
I
CC
Power Supply Current 135 mA
I
CCA
Analog Supply Current 25 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 mV
V
IL
Input Low Voltage -0.3 0.8 mV
I
IH
Input High Current
nOE0, nOE1, FS1,
BYPASS
V
CC
= V
IN
= 3.63V 150 µA
FS0, PLL_BW 5 µA
I
IL
Input Low Current
nOE0, nOE1, FS1,
BYPASS
V
CC
= 3.63V, V
IN
= 0V -5 µA
FS0, PLL_BW -150 µA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
49.8°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DB306BLLFT

Mfr. #:
Buy 9DB306BLLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVPECL Output PCI- Express Buffer
Lifecycle:
New from this manufacturer.
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