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9DB306BLLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20167
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
FIGURE 1. POWER SUPPLY FILTERING
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 9DB306 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
CC
and V
CCA
should be individually connected to
the power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic V
CC
pin and also shows that V
CCA
requires that an additional 24Ω resistor
along with a 10µF bypass capacitor be connected to the V
CCA
pin.
V
CC
V
CCA
3.3V
24Ω
10µF.01µF
.01µF
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20168
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING and VOH must meet the
V
PP and VCMR input requirements. Figures 3A to 3E show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN
IDT LVHSTL DRIVER
only. Please consult with the vendor of the driver component to
confi rm the driver termination requirements. For example in Figure
3A, the input termination applies for IDT LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20169
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock com-
ponent process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 4B. LVPECL OUTPUT T ERMINATIONFIGURE 4A. LVPECL OUTPUT T ERMINATION
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DB306BLLFT

Mfr. #:
Buy 9DB306BLLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVPECL Output PCI- Express Buffer
Lifecycle:
New from this manufacturer.
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