9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20164
TABLE 5A. AC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = 0°C TO 70°C
TABLE 4D. LVPECL DC CHARACTERISTICS, V
CC
= 3.3V±10%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 2.0 V
CC
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 140 MHz
tsk(o) Output Skew; NOTE 1, 2 55 135 ps
tjit(cc) Cycle-to-Cycle Jitter, NOTE 2 25 ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
Integration Range:
1.5MHz - 22MHz
3ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle 48 52 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
TABLE 5B. AC CHARACTERISTICS, V
CC
= 3.3V±10%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 140 MHz
tsk(o) Output Skew; NOTE 1, 2 25 100 ps
tjit(cc) Cycle-to-Cycle Jitter, NOTE 2 30 ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
Integration Range:
1.5MHz - 22MHz
3ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle 47 53 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20165
TYPICAL PHASE NOISE AT 100MHZ
The illustrated phase noise plot was taken using a low phase noise
signal generator, the noise fl oor of the signal generator is less than
that of the device under test.
Using this confi guration allows one to see the true spectral purity or
phase noise performance of the PLL in the device under test. Due
to the tracking ability of a PLL, it will track the input signal up to its
loop bandwidth. Therefore, if the input phase noise is greater than
that of the PLL, it will increase the output phase noise performance
of the device. It is recommended that the phase noise performance
of the input is verifi ed in order to achieve the above phase noise
performance.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 3ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER
dBc
Hz
Phase Noise Result by adding
PCI Express™ Filter to raw data
PCI Express™ Filter
Raw Phase Noise Data
9DB306 Data Sheet
©2016 Integrated Device Technology, Inc Revision C February 18, 20166
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME

9DB306BLLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVPECL Output PCI- Express Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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