PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS 10 FEBRUARY 22, 2016
954206B DATASHEET
Electrical Characteristics – REF-14.318MHz
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2
Clock period T
p
eriod
14.318MHz output nominal 69.8270 69.8550 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Output High Current I
OH
V
OH
@MIN = 1.0 V,
V
OH
@MAX = 3.135 V
-29 -23 mA 1
Output Low Current I
OL
V
OL
@MIN = 1.95 V,
V
OL
@MAX = 0.4 V
29 27 mA 1
Edge Rate t
slewr/f
Rising/Falling edge rate 1 2 4 V/ns 1
Rise Time t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 1.6 2 ns 1
Fall Time t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V 0.5 2 2 ns 1
Skew t
sk1
V
T
= 1.5 V 500 ps 1
Duty Cycle d
t1
V
T
= 1.5 V 45 53 55 % 1
Jitter t
j
c
y
c-c
y
c
V
T
= 1.5 V 750 1000 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7
Ω
(Rs is used in USB48MHz test only)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
FEBRUARY 22, 2016 11 PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
954206B DATASHEET
General SMBus Serial Interface Information for 954206B
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
D3
(H)
D2
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS 12 FEBRUARY 22, 2016
954206B DATASHEET
I
2
C Table: Output Control Register
Control
Function
Bit 7
CPUCLK2_ITP/PCIEX6
Enable
Output Enable RW 1
Bit 6
PCIEX5 Enable Output Enable RW 1
Bit 5
PCIEX4 Enable Output Enable RW 1
Bit 4
SATACLK Enable Output Enable RW 1
Bit 3
PCIEX3 Enable Output Enable RW 1
Bit 2
PCIEX2 Enable Output Enable RW 1
Bit 1
PCIEX1 Enable Output Enable RW 1
Bit 0
LCDCLK/PCIEX0 Enable Output Enable RW 1
I
2
C Table: Spread and Output Control Register
Control
Function
Bit 7
Test Clock Mode Entry Test Mode RW 0
Bit 6
DOT_96MHz Enable Output Enable RW 1
Bit 5
USB_48MHz Enable Output Enable RW 1
Bit 4
REF_0 Enable Output Enable RW 1
Bit 3
LCDCLK/PCIEX0 Spectrum
Mode
Spread Control RW 1
Bit 2
CPUCLK1 Output Enable RW 1
Bit 1
CPUCLK0 Output Enable RW 1
Bit 0
Spread Spectrum Mode Spread Control for PLL1 RW 0
I
2
C Table: Output Control Register
Control
Function
Bit 7
PCICLK5 Output Enable RW 1
Bit 6
PCICLK4 Output Enable RW 1
Bit 5
PCICLK3 Output Enable RW 1
Bit 4
PCICLK2 Output Enable RW 1
Bit 3
Test Mode Selection Test Mode Selection RW 0
Bit 2
PCI_STOP
Stop all PCI, PCIEX and
SATA clocks
RW 1
Bit 1
PCI_F0 Enable Output Enable RW 1
Bit 0
PCI_F1 Enable Output Enable RW 1
I
2
C Table: Output Control Register
Control
Function
Bit 7
PCIEX6 RW 0
Bit 6
PCIEX5 RW 0
Bit 5
PCIEX4 RW 0
Bit 4
SATACLK RW 0
Bit 3
PCIEX3 RW 0
Bit 2
PCIEX2 RW 1
Bit 1
PCIEX1 RW 1
Bit 0
PCIEX0 RW 1
Enable
Disable Enable
Disable Enable
OFF ON
Enable
Disable Enable
Disable
-
Disable Enable
Disable Enable
Disable
-
-
Enable
Disable Enable
-
-
-
-
- Disable Enable
Enable
Enable
OFF
Disable
Disable
ON
PWD01Byte 1 Pin # Name Type
-
-
-
-
-
-
Disable Enable
01
Disable Enable
PWD
-
Byte 0 Pin # Name Type
- Disable
Free Running
Free Running
-
Free Running
-
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCIEX clocks
Stoppable
Stoppable
Free Running
Stoppable
-
-
Enable
Stoppable
Disable
Disable
-
-
Enable
PWD
PWD
Stoppable
Enable
1
Enable
Stoppable
Disable
Stoppable
Enable
0
Disable
Byte 2 Pin # Name Type
-
0
Disable
Byte 3
Hi-Z
Pin # Name Type
Disable
-
-
-
-
-
-
-
-
-
Disable
Free Running Stoppable
Free Running
Enable
1
REF/N
Free Running
Free Running
Enable

954206BGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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