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954206BGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
FEBRUARY 22, 2016 13 PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
954206B DATASHEET
I
2
C Table:Output Control Register
Control
Function
Bit 7
REF_1 Enable Output Enable RW 1
Bit 6
96MHz
Driven in PD
RW 1
Bit 5
REF_0 STRENGTH Strength Programming RW 1
Bit 4
PCI_F1 RW 1
Bit 3
PCI_F0 RW 1
Bit 2
CPUCLK2_ITP RW 1
Bit 1
CPUCLK1 RW 1
Bit 0
CPUCLK0 RW 1
I
2
C Table:Output Control Register
Control
Function
Bit 7
PCI_STOP Drive Mode Driven in PCI_STOP# RW 0
Bit 6
CPUCLK2_ITP_STOP Drive
Mode
RW 0
Bit 5
CPUCLK1_STOP Drive
Mode
RW 0
Bit 4
CPUCLK0_STOP Drive
Mode
RW 0
Bit 3
PCIEX (6:0) Drive Mode RW 0
Bit 2
CPUCLK2_ITP_PD Drive
Mode
RW 0
Bit 1
CPUCLK[1:0] PD Drive
Mode
RW 0
Bit 0
ITP_EN PCIEX/CPU_ITP select RW latch
I
2
C Table: Output Control Register
Control
Function
Bit 7
SS4 LCDCLK Spread Prog Bit 4 RW 0
Bit 6
SS3 LCDCLK Spread Prog Bit 3 RW 1
Bit 5
SS2 LCDCLK Spread Prog Bit 2 RW 0
Bit 4
SS1 LCDCLK Spread Prog Bit 1 RW 0
Bit 3
SS0 LCDCLK Spread Prog Bit 0 RW 0
Bit 2
FSLC Freq Select Bit 2 RW Latched
Bit 1
FSLB Freq Select Bit 1 RW Latched
Bit 0
FSLA Freq Select Bit 0 RW Latched
I
2
C Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3 R x
Bit 6
RID2 R x
Bit 5
RID1 R x
Bit 4
RID0 R x
Bit 3
VID3 R 0
Bit 2
VID2 R 0
Bit 1
VID1 R 0
Bit 0
VID0 R 1
-
-
VENDOR ID
--
- --
-
- --
- --
1PWD
-
REVISION ID
--
- --
-
Stoppable
Free Running
Byte 7 Pin # Name Type 0
Name
-
-
- -
Driven
Driven Hi-Z
Driven
-
Pin #
2X
1
Hi-Z
Hi-Z
Stoppable
Stoppable
Stoppable
Driven in Powerdown (PD)
Allow assertion of
CPU_STOP# to stop CPUCLK
outputs
-
Name
-
-
-
Driven in CPU_STOP#
Allow assertion of
PCI_STOP# or setting of
See Table 1: PLL1 Frequency Selection
Table
Free Running
Hi-Z
0
Driven
See Table 2: LCDCLK Freq Sel
Type
Free Running
Hi-Z
Disable
Driven
1
96Mhz 100Mhz
Driven
Driven
Free Running
Driven
PCIEX
Enable
Stoppable
Hi-Z
PWD
Hi-Z
1
Hi-Z
CPU_ITP
Type
PWDType 0
Free Running
0
1X
PWD
-
-
-
-
-
-
Byte 5
-
-
Pin #
-
-
-
Byte 4
-
-
-
-
-
-
-
Byte 6 Pin # Name
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS 14 FEBRUARY 22, 2016
954206B DATASHEET
I
2
C Table: Byte Count Register
Control
Function
Bit 7
BC7 RW 0
Bit 6
BC6 RW 0
Bit 5
BC5 RW 0
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 1
Bit 1
BC1 RW 1
Bit 0
BC0 RW 1
I
2
C Table: Watchdog Timer Register
Control
Function
Bit 7
WDH_EN Watchdog Hard Alarm Enable RW 0
Bit 6
WDS_EN Watchdog Soft Alarm Enable RW 0
Bit 5
WD Hard Status WD Hard Alarm Status R X
Bit 4
WD Soft Status WD Soft Alarm Status R X
Bit 3
WDTCtrl
Watch Dog Time base
Control
RW 0
Bit 2
WD2 WD Timer Bit 2 RW 1
Bit 1
WD1 WD Timer Bit 1 RW 1
Bit 0
WD0 WD Timer Bit 0 RW 1
I
2
C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 7
M/N_EN PLLM/N Programming Enable RW 0
Bit 6
LCDCLK/PCIEX0 SEL SELPCIEX0/LCDCLK# RW latch
Bit 5
REQ_SEL REQ_SEL RW latch
Bit 4
LCDCLK/PCIEX0 Driven in PD RW 0
Bit 3
WD Safe Freq Source WD Safe Freq Source RW 0
Bit 2
WD SFC RW 0
Bit 1
WD SFB RW 0
Bit 0
WD SFA RW 0
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8 N Divider Prog bit 8 RW X
Bit 6
N Div 9 N Divider Prog bit 9 RW X
Bit 5
M Div5 RW X
Bit 4
M Div4 RW X
Bit 3
M Div3 RW X
Bit 2
M Div2 RW X
Bit 1
M Div1 RW X
Bit 0
M Div0 RW X
M Divider Programming bits
Alarm
LCDCLK PCIEX0
-
-
PWDTypeName
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
10
PWD
-
PCIEX5 PEREQ
Byte 10 Pin # Name
Disable
-
Normal
Normal
-
-
Latch
Inputs/Byte6[2:0]
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
290ms Base
B10b(2:0)
PWD
PWD
1
1Name Type 0
Byte Count Programming
b(7:0)
-
-
-
-
-
Byte 8 Name Type
-
-
-
-
-
-
-
-
-
-
-
Byte 9 Pin #
-
-
-
-
-
-
-
-
-
-
Pin #
Byte 11 Pin #
0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Type 0 1
1160ms Base
Enable
Disable
Driven Hi-Z
Disable Enable
Alarm
Enable
FEBRUARY 22, 2016 15 PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
954206B DATASHEET
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div7 RW X
Bit 6
N Div6 RW X
Bit 5
N Div5 RW X
Bit 4
N Div4 RW X
Bit 3
N Div3 RW X
Bit 2
N Div2 RW X
Bit 1
N Div1 RW X
Bit 0
N Div0 RW X
I
2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
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2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
Reserved Reserved R 0
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
I
2
C Table: Output Divider Control Register
Control
Function
Bit 7
PCIEX Div3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X
Bit 6
PCIEX Div2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X
Bit 5
PCIEX Div1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X
Bit 4
PCIEX Div0 RW 0011:/15 0111:/30 1011:/60 1111:/120 X
Bit 3
CPU Div3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X
Bit 2
CPU Div2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X
Bit 1
CPU Div1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X
Bit 0
CPU Div0 RW 0011:/15 0111:/30 1011:/60 1111:/120 X
1Type
Spread Spectrum
Programming b(7:0)
N Divider Programming
b(8:0)
1
1
0
-
Type
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
1Byte 12
-
-
-
CPUDivider Ratio
Programming Bits
PCIEX Divider Ratio
Programming Bits
PWD
Name Type 0
PWDName Type
Name
PWD
0
-
-
-
NamePin #
-
-
-
-
-
PWD0
Byte 13 Pin #
-
Byte 14 Pin #
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
-
-
-
Byte 15
-
-
-
Spread Spectrum
Programming b(14:8)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

954206BGLF

Mfr. #:
Buy 954206BGLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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