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954206BGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS 16 FEBRUARY 22, 2016
954206B DATASHEET
I
2
C Table: PEREQ# Control Register
Control
Function
Bit 7
Reserved Reserved RW 0
Bit 6
PCIEX4 is controlled RW 1
Bit 5
PCIEX3 is controlled RW 0
Bit 4
PCIEX1 is controlled RW 0
Bit 3
Reserved Reserved RW 0
Bit 2
SATACLK is controlled RW 1
Bit 1
PCIEX2 is controlled RW 0
Bit 0
PCIEX0 is controlled RW 0
I
2
C Table: PLL 2 VCO Frequency Control Register
Control
Function
Bit 7
N Div8 N Divider Prog bit 8 RW X
Bit 6
N Div9 N Divider Prog bit 9 RW X
Bit 5
M Div5 RW X
Bit 4
M Div4 RW X
Bit 3
M Div3 RW X
Bit 2
M Div2 RW X
Bit 1
M Div1 RW X
Bit 0
M Div0 RW X
I
2
C Table: PLL 2 VCO Frequency Control Register
Control
Function
Bit 7
N Div7 RW X
Bit 6
N Div6 RW X
Bit 5
N Div5 RW X
Bit 4
N Div4 RW X
Bit 3
N Div3 RW X
Bit 2
N Div2 RW X
Bit 1
N Div1 RW X
Bit 0
N Div0 RW X
I
2
C Table: PLL 2 Spread Spectrum Control Register
Control
Function
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
1
Not Controlled Controlled
1
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
Controlled
Not Controlled Controlled
Not Controlled
--
Name Type
M Divider Programming bits
Type
-
-
Byte 19 Pin #
0
0
Spread Spectrum
Programming b(7:0)
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
PWDName Type 0 1
PWD
PWD01
PWD
Pin #Byte 16
-
-
Type
-
-
-
-
Pin # Name
PEREQ2# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ2# is high.
PEREQ1# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ1# is high.
-
-
-
-
-
-
Byte 17
-
-
-
-
-
-
-
-
-
-
Pin # Name
-
-
-
-
-
-
-
N Divider Programming
b(8:0)
-
Byte 18
Controlled
Controlled
Controlled
-
Not Controlled
Not Controlled
Not Controlled
-
FEBRUARY 22, 2016 17 PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
954206B DATASHEET
Test Clarification Table
I
2
C Table: PLL2 Spread Spectrum Control Register
Control
Function
Bit 7
Reserved Reserved R 0
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
-
-
-
0
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Name
Spread Spectrum
Programming b(14:8)
PWDType 1
--
-
-
-
-
Byte 20 Pin #
-
Comments
FSLC/TES
T_SEL
HW PIN
FSLB/TES
T_MODE
HW PIN
TEST
ENTRY
BIT
W1b7
REF/N or
HI-Z
W2b3
OUTPUT
0X0XNORMAL
10X0HI-Z
10X1REF/N
11X0REF/N
11X1REF/N
0X10HI-Z
0X11REF/N
W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
W2b3: 1= REF/N, Default = 0 (HI-Z)
HW SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through W1b7.
If test mode is invoked by W1b7,
only
W2b3
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS 18 FEBRUARY 22, 2016
954206B DATASHEET
Package Outline and Dimensions (56-pin TSSOP)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

954206BGLF

Mfr. #:
Buy 954206BGLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
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