PIN # PIN NAME TYPE DESCRIPTION
29 GND PWR Ground pin.
30 PCIEXC4 OUT Complement clock of differential PCI_Express pair.
31 PCIEXT4 OUT True clock of differential PCI_Express pair.
32 PEREQ2#*/PCIEXC5 I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
33 PEREQ1#*/PCIEXT5 I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
34 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
35 CPUCLKC2_ITP/PCIEXC6 OUT
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
36 CPUCLKT2_ITP/PCIEXT6 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
37 VDDA PWR 3.3V power for the PLL core.
38 GNDA PWR Ground pin for the PLL core.
39 IREF OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
40 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
43 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45 GND PWR Ground pin.
46 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
47 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
49 X2 OUT Crystal output, Nominally 14.318MHz
50 X1 IN Crystal input, Nominally 14.318MHz.
51 GND PWR Ground pin.
52 REF0 OUT 14.318 MHz reference clock.
53 REF1/FSLC/TEST_SEL I/O
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
54 CPU_STOP# IN Stops all CPUCLK, except those set to be free running clocks
55 PCI/SRC_STOP# IN
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
56 PCICLK2/REQ_SEL** I/O 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
