I2C Registers VV6501
40/60
[0x25] - Clock divider setting
[0x2C -0x2D] - Dark line pixel offset
[0x2E] - Dark line offset cancellation setup register
Bit Function Default Comment
[7:4] RESERVED
[3:0] Clock divider setting 0 0000 - Divide clock by 1
0001 - Divide clock by 2
001x - Divide clock by 4
010x - Divide clock by 6
011x - Divide clock by 8
100x - Divide clock by 10
101x - Divide clock by 12
110x - Divide clock by 14
111x - Divide clock by 16
Bit Function Default Comment
[7:0] LS Dark line pixel offset 0 This register contains a fixed offset that can be
applied to the digitised pixels in the digital output
coding block. The offset is a 2’s complement
number, giving an offset range -1024,+1023.
[2:0] MS Dark line pixel offset
Bit Function Default Comment
7 RESERVED
[6:4] RESERVED
3 Dark leaky integrator time
constant
00 - Fast
1 - Slow
2 RESERVED
[1:0] Dark line offset cancellation 01 00 - Accumulate dark pixels, calculate dark pixel
average and report, but don’t apply anything to
data stream
01 - Accumulate dark pixels, calculate dark pixel
average, report and apply internally calculated
offset to data stream
11 - Accumulate dark pixels, calculate dark pixel
average and report, but apply an externally
calculated offset
