MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
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The MAX1652–MAX1655 contain nine major circuit
blocks, which are shown in Figure 2:
PWM Controller Blocks:
• Multi-Input PWM Comparator
• Current-Sense Circuit
• PWM Logic Block
• Dual-Mode Internal Feedback Mux
• Gate-Driver Outputs
• Secondary Feedback Comparator
Bias Generator Blocks:
• +5V Linear Regulator
• Automatic Bootstrap Switchover Circuit
• +2.50V Reference
These internal IC blocks aren’t powered directly from
the battery. Instead, a +5V linear regulator steps down
the battery voltage to supply both the IC internal rail (VL
pin) as well as the gate drivers. The synchronous-
switch gate driver is directly powered from +5V VL,
while the high-side-switch gate driver is indirectly pow-
ered from VL via an external diode-capacitor boost cir-
cuit. An automatic bootstrap circuit turns off the +5V
linear regulator and powers the IC from its output volt-
age if the output is above 4.5V.
PWM Controller Block
The heart of the current-mode PWM controller is a
multi-input open-loop comparator that sums three sig-
nals: output voltage error signal with respect to the ref-
erence voltage, current-sense signal, and slope
compensation ramp (Figure 3). The PWM controller is a
direct summing type, lacking a traditional error amplifi-
er and the phase shift associated with it. This direct-
summing configuration approaches the ideal of
cycle-by-cycle control over the output voltage.
Under heavy loads, the controller operates in full PWM
mode. Each pulse from the oscillator sets the main
PWM latch that turns on the high-side switch for a peri-
od determined by the duty factor (approximately
V
OUT
/V
IN
). As the high-side switch turns off, the syn-
chronous rectifier latch is set. 60ns later the low-side
switch turns on, and stays on until the beginning of the
next clock cycle (in continuous mode) or until the
inductor current crosses zero (in discontinuous mode).
Under fault conditions where the inductor current
exceeds the 100mV current-limit threshold, the high-
side latch resets and the high-side switch turns off.
If the load is light in Idle Mode (SKIP = low), the induc-
tor current does not exceed the 25mV threshold set by
the Idle Mode comparator. When this occurs, the con-
troller skips most of the oscillator pulses in order to
reduce the switching frequency and cut back gate-
charge losses. The oscillator is effectively gated off at
light loads because the Idle Mode comparator immedi-
ately resets the high-side latch at the beginning of each
cycle, unless the feedback signal falls below the refer-
ence voltage level.
When in PWM mode, the controller operates as a fixed-
frequency current-mode controller where the duty ratio
is set by the input/output voltage ratio. The current-
mode feedback system regulates the peak inductor
current as a function of the output voltage error signal.
Since the average inductor current is nearly the same
as the peak current, the circuit acts as a switch-mode
transconductance amplifier and pushes the second out-
put LC filter pole, normally found in a duty-factor-
controlled (voltage-mode) PWM, to a higher frequency.
To preserve inner-loop stability and eliminate regenera-
tive inductor current “staircasing,” a slope-compensa-
tion ramp is summed into the main PWM comparator to
reduce the apparent duty factor to less than 50%.
The relative gains of the voltage- and current-sense
inputs are weighted by the values of current sources
that bias three differential input stages in the main PWM
comparator (Figure 4). The relative gain of the voltage
comparator to the current comparator is internally fixed
at K = 2:1. The resulting loop gain (which is relatively
low) determines the 2% typical load regulation error.
The low loop-gain value helps reduce output filter
capacitor size and cost by shifting the unity-gain
crossover to a lower frequency.
The output filter capacitor C2 sets a dominant pole in
the feedback loop. This pole must roll off the loop gain
to unity before the zero introduced by the output
capacitor’s parasitic resistance (ESR) is encountered
(see
Design Procedure
section). A 12kHz pole-zero
cancellation filter provides additional rolloff above the
unity-gain crossover. This internal 12kHz lowpass com-
pensation filter cancels the zero due to the filter capaci-
tor’s ESR. The 12kHz filter is included in the loop in
both fixed- and adjustable-output modes.
Synchronous-Rectifier Driver (DL Pin)
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode with
a low-resistance MOSFET switch. The synchronous rec-
tifier also ensures proper start-up of the boost-gate driv-
er circuit. If you must omit the synchronous power
MOSFET for cost or other reasons, replace it with a
small-signal MOSFET such as a 2N7002.
If the circuit is operating in continuous-conduction mode,
the DL drive waveform is simply the complement of the
DH high-side drive waveform (with controlled dead
time to prevent cross-conduction or “shoot-through”).
