MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
16 ______________________________________________________________________________________
an action that “boosts” the 5V gate-drive signal above
the battery voltage.
Ringing seen at the high-side MOSFET gate (DH) in
discontinuous-conduction mode (light loads) is a natur-
al operating condition caused by the residual energy in
the tank circuit formed by the inductor and stray capac-
itance at the switching node LX. The gate-driver nega-
tive rail is referred to LX, so any ringing there is directly
coupled to the gate-drive output.
Current-Limiting and
Current-Sense Inputs (CSH and CSL)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor must be sized for
80mV/R1 to guarantee enough load capability, while
components must be designed to withstand continuous
current stresses of 120mV/R1.
For breadboarding purposes or very-high-current appli-
cations, it may be useful to wire the current-sense inputs
with a twisted pair rather than PC traces.
Oscillator Frequency and
Synchronization (SYNC Pin)
The SYNC input controls the oscillator frequency.
Connecting SYNC to GND or to VL selects 150kHz
operation; connecting SYNC to REF selects 300kHz.
SYNC can also be used to synchronize with an external
5V CMOS clock generator. SYNC has a guaranteed
190kHz to 340kHz capture range.
300kHz operation optimizes the application circuit for
component size and cost. 150kHz operation provides
increased efficiency and improved low-duty factor
operation (see
Dropout Operation
section).
Dropout Operation
Dropout (low input-output differential operation) is en-
hanced by stretching the clock pulse width to increase
the maximum duty factor. The algorithm follows: if the out-
put voltage (V
OUT
) drops out of regulation without the
current limit having been reached, the controller skips an
off-time period (extending the on-time). At the end of the
cycle, if the output is still out of regulation, another off-time
period is skipped. This action can continue until three off-
time periods are skipped, effectively dividing the clock
frequency by as much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating fre-
quency raises the maximum duty factor above 98%.
Low-Noise Mode (SKIP Pin)
The low-noise mode (SKIP = high) is useful for minimiz-
ing RF and audio interference in noise-sensitive appli-
cations such as audio-equipped systems, cellular
phones, RF communicating computers, and electro-
magnetic pen-entry systems. See the summary of oper-
ating modes in Table 3. SKIP can be driven from an
external logic signal.
The MAX1653 and MAX1655 can reduce interference
due to switching noise by ensuring a constant switch-
ing frequency regardless of load and line conditions,
thus concentrating the emissions at a known frequency
outside the system audio or IF bands. Choose an oscil-
lator frequency where harmonics of the switching fre-
quency don’t overlap a sensitive frequency band. If
necessary, synchronize the oscillator to a tight-toler-
ance external clock generator.
The low-noise mode (SKIP = high) forces two changes
upon the PWM controller. First, it ensures fixed-frequen-
cy operation by disabling the minimum-current com-
parator and ensuring that the PWM latch is set at the
beginning of each cycle, even if the output is in regula-
tion. Second, it ensures continuous inductor current
