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MAX1653EEE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
22 ______________________________________________________________________________________
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see
Inductor Value
section for def-
initions of parameters). Set the value of the current-
sense resistor at 80mV / I
TOTAL
.
P
TOTAL
=the sum of the output power from
all outputs
I
TOTAL
=P
TOTAL
/ V
OUT
= the equivalent output
current referred to V
OUT
V
OUT
(V
IN(MAX)
- V
OUT
)
L(primary) = —————————————
V
IN(MAX)
x f x I
TOTAL
x LIR
V
SEC
+ V
FWD
Turns Ratio N = ——————————————
V
OUT(MIN)
+ V
RECT
+ V
SENSE
where: V
SEC
is the minimum required rectified
secondary-output voltage
V
FWD
is the forward drop across the
secondary rectifier
V
OUT(MIN)
is the
minimum
value of the main
output voltage (from the
Electrical
Characteristics
)
V
RECT
is the on-state voltage drop across the
synchronous-rectifier MOSFET
V
SENSE
is the voltage drop across the sense
resistor
In positive-output (MAX1652) applications, the trans-
former secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
voltage to obtain V
SEC
.
______Selecting Other Components
MOSFET Switches
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifi-
cations at V
GS
= 4.5V. Lower gate threshold specs are
better (i.e., 2V max rather than 3V max). Drain-source
breakdown voltage ratings must at least equal the max-
imum input voltage, preferably with a 20% derating
factor. The best MOSFETs will have the lowest on-resis-
tance per nanocoulomb of gate charge. Multiplying
R
DS(ON)
x Q
G
provides a meaningful figure by which to
compare various MOSFETs. Newer MOSFET process
technologies with dense cell structures generally give
the best performance. The internal gate drivers can tol-
erate more than 100nC total gate charge, but 70nC is a
more practical upper limit to maintain best switching
times.
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
I
2
R losses are distributed between Q1 and Q2 accord-
ing to duty factor (see the equations below). Switching
losses affect the upper MOSFET only, since the
Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. Gate-charge losses are
dissipated by the driver and don’t heat the MOSFET.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. The worst-case dissi-
pation for the high-side MOSFET occurs at the minimum
battery voltage, and the worst-case for the low-side
MOSFET occurs at the maximum battery voltage.
PD (upper FET) = I
LOAD
2
x R
DS(ON)
x DUTY
V
IN
x C
RSS
+ V
IN
x I
LOAD
x f x
(
––––––––––– +20ns
)
I
GATE
PD (lower FET) = I
LOAD
2
x R
DS(ON)
x (1 - DUTY)
DUTY = (V
OUT
+ V
Q2
) / (V
IN
- V
Q1
+ V
Q2
)
where the on-state voltage drop V
Q_
= I
LOAD
x R
DS(ON)
C
RSS
=MOSFET reverse transfer capacitance
I
GATE
=DH driver peak output current capability
(1A typically)
20ns = DH driver inherent rise/fall time
Under output short circuit, the synchronous-rectifier
MOSFET suffers extra stress and may need to be over-
sized if a continuous DC short circuit must be tolerated.
During short circuit, Q2’s duty factor can increase to
greater than 0.9 according to:
Q2 DUTY (short circuit) = 1 - [V
Q2
/ (V
IN(MAX)
- V
Q1 +
V
Q2
)]
where the on-state voltage drop V
Q
= (120mV / R
SENSE
)
x R
DS(ON).
Rectifier Diode D1
Rectifier D1 is a clamp that catches the negative induc-
tor swing during the 60ns dead time between turning
off the high-side MOSFET and turning on the low-side.
D1 must be a Schottky type in order to prevent the
lossy parasitic MOSFET body diode from conducting. It
is acceptable to omit D1 and let the body diode clamp
the negative inductor swing, but efficiency will drop one
or two percent as a result. Use an MBR0530 (500mA
rated) type for loads up to 1.5A, a 1N5819 type for
loads up to 3A, or a 1N5822 type for loads up to 10A.
D1’s rated reverse breakdown voltage must be at least
equal to the maximum input voltage, preferably with a
20% derating factor.
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 23
Boost-Supply Diode D2
A 10mA to 100mA Schottky diode or signal diode such
as a 1N4148 works well for D2 in most applications. If
the input voltage can go below 6V, use a Schottky
diode for slightly improved efficiency and dropout char-
acteristics. Don’t use large power diodes such as
1N5817 or 1N4001, since high junction capacitance
can cause VL to be pumped up to excessive voltages.
Rectifier Diode D3
(Transformer Secondary Diode)
The secondary diode in coupled-inductor applications
must withstand high flyback voltages greater than 60V,
which usually rules out most Schottky rectifiers.
Common silicon rectifiers such as the 1N4001 are also
prohibited, as they are far too slow. This often makes
fast silicon rectifiers such as the MURS120 the only
choice. The flyback voltage across the rectifier is relat-
ed to the V
IN
-V
OUT
difference according to the trans-
former turns ratio:
V
FLYBACK
= V
SEC
+ (V
IN
- V
OUT
) x N
where: N is the transformer turns ratio SEC/PRI
V
SEC
is the maximum secondary DC output voltage
V
OUT
is the primary (main) output voltage
Subtract the main output voltage (V
OUT
) from V
FLYBACK
in this equation if the secondary winding is returned to
V
OUT
and not to ground. The diode reverse breakdown
rating must also accommodate any ringing due to leak-
age inductance. D3’s current rating should be at least
twice the DC load current on the secondary output.
_____________Low-Voltage Operation
Low input voltages and low input-output differential volt-
ages each require some extra care in the design. Low
absolute input voltages can cause the VL linear regula-
tor to enter dropout, and eventually shut itself off. Low
input voltages relative to the output (low V
IN
-V
OUT
differ-
ential) can cause bad load regulation in multi-output fly-
back applications. See
Transformer Design
section.
Finally, low V
IN
-V
OUT
differentials can also cause the
output voltage to sag when the load current changes
abruptly. The amplitude of the sag is a function of induc-
tor value and maximum duty factor (D
MAX
an
Electrical
Characteristics
parameter, 98% guaranteed over tem-
perature at f = 150kHz) as follows:
(I
STEP
)
2
x L
V
SAG
= ———————————————
2 x C
OUT
x (V
IN(MIN)
x D
MAX
- V
OUT
)
The cure for low-voltage sag is to increase the value of
the output capacitor. For example, at V
IN
= 5.5V, V
OUT
= 5V, L = 10µH, f = 150kHz, a total capacitance of
660µF will prevent excessive sag. Note that only the
capacitance requirement is increased and the ESR
requirements don’t change. Therefore, the added
capacitance can be supplied by a low-cost bulk
capacitor in parallel with the normal low-ESR capacitor.
Table 4 summarizes low-voltage operational issues.
Table 4. Low-Voltage Troubleshooting
Supply VL from an external source other
than V
BATT
, such as the system 5V supply.
VL output is so low that it hits the
VL UVLO threshold at 4.2V max.
Low input voltage, <4.5V
Won’t start under load or
quits before battery is
completely dead
Use a small 20mA Schottky diode for
boost diode D2. Supply VL from an
external source.
VL linear regulator is going into
dropout and isn’t providing
good gate-drive levels.
Low input voltage, <5V
High supply current,
poor efficiency
Reduce f to 150kHz. Reduce secondary
impedances—use Schottky if possible.
Stack secondary winding on main output.
Not enough duty cycle left to
initiate forward-mode operation.
Small AC current in primary can’t
store energy for flyback operation.
Low V
IN
-V
OUT
differential,
V
IN
< 1.3 x V
OUT
(main)
Secondary output won’t
support a load
Increase the minimum input voltage or
ignore.
Normal function of internal low-
dropout circuitry.
Low V
IN
-V
OUT
differential,
<0.5V
Unstable—jitters between
two distinct duty factors
Reduce f to 150kHz. Reduce MOSFET
on-resistance and coil DCR.
Maximum duty-cycle limits
exceeded.
Low V
IN
-V
OUT
differential,
<0.5V
Dropout voltage is too
high (V
OUT
follows V
IN
as
V
IN
decreases)
Increase bulk output capacitance per
formula above. Reduce inductor value.
Limited inductor-current slew
rate per cycle.
Low V
IN
-V
OUT
differential,
<1V
Sag or droop in V
OUT
under step load change
SOLUTION
ROOT CAUSECONDITIONSYMPTOM
__________Applications Information
Heavy-Load Efficiency Considerations
The major efficiency loss mechanisms under loads (in
the usual order of importance) are:
• P(I
2
R), I
2
R losses
• P(gate), gate-charge losses
• P(diode), diode-conduction losses
• P(tran), transition losses
• P(cap), capacitor ESR losses
• P(IC), losses due to the operating supply current
of the IC
Inductor-core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
Efficiency = P
OUT
/ P
IN
x 100%
= P
OUT
/ (P
OUT
+ P
TOTAL
) x 100%
P
TOTAL
= P(I
2
R) + P(gate) + P(diode) + P(tran) +
P(cap) + P(IC)
P(I
2
R) = (I
LOAD
)
2
x (R
DC
+ R
DS(ON)
+ R
SENSE
)
where R
DC
is the DC resistance of the coil, R
DS(ON)
is
the MOSFET on-resistance, and R
SENSE
is the current-
sense resistor value. The R
DS(ON)
term assumes identi-
cal MOSFETs for the high- and low-side switches
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX1652 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
qG is twice the data sheet value of an individual
MOSFET. If V
OUT
is set to less than 4.5V, replace VL in
this equation with V
BATT
. In this case, efficiency can be
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
P(diode) =diode conduction losses
=I
LOAD
x V
FWD
x t
D
x f
where t
D
is the diode conduction time (120ns typ) and
V
FWD
is the forward voltage of the Schottky.
PD(tran) = transition loss =
V
BATT
x C
RSS
V
BATT
x I
LOAD
x f x
(
——————— + 20ns
)
I
GATE
where C
RSS
is the reverse transfer capacitance of the
high-side MOSFET (a data sheet parameter), I
GATE
is
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver.
P(cap) = input capacitor ESR loss = (I
RMS
)
2
x R
ESR
where I
RMS
is the input ripple current as calculated in the
Input Capacitor Value
section of the
Design Procedure.
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
and I
2
R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
__PC Board Layout Considerations
Good PC board layout is
required
to achieve specified
noise, efficiency, and stability performance. The PC
board layout artist must be provided with explicit
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX1653, MAX796, and MAX797 EV kit manuals for
examples. A ground plane is essential for optimum per-
formance. In most applications, the circuit will be locat-
ed on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high-current connections, the bottom layer for quiet
connections (REF, SS, GND), and the inner layers for
an uninterrupted ground plane. Use the following step-
by-step guide.
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
lengths (see Figure 9).
Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
Priority 3: Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm max length. D1 anode to
Q2: 5mm max length LX node (Q1
source, Q2 drain, D1 cathode, inductor):
15mm max length
Ideally, surface-mount power components are
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
24 ______________________________________________________________________________________
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

MAX1653EEE

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