MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
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Pin Description
Dual Mode is a trademark of Maxim Integrated Products.
SKIP
(MAX1653/
MAX1655)
Disables pulse-skipping mode when high. Connect to GND for normal use. Don’t leave SKIP unconnected.
With SKIP
grounded, the device will
automatically
change from pulse-skipping operation to full PWM opera-
tion when the load current exceeds approximately 30% of maximum (Table 3).
16 DH
High-Side Gate-Drive Output. Normally drives the main buck switch. DH is a floating driver output that swings
from LX to BST, riding on the LX switching-node voltage.
15 LX Switching Node (inductor) Connection. Can swing 2V below ground without hazard.
14 BST Boost Capacitor Connection for High-Side Gate Drive (0.1µF)
13 DL Low-Side Gate-Drive Output. Normally drives the synchronous-rectifier MOSFET. Swings from 0V to VL.
NAME FUNCTION
1 SS Soft-Start Timing Capacitor Connection. Ramp time to full current limit is approximately 1ms/nF.
2
SECFB
(MAX1652/
MAX1654)
Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output.
Don’t leave SECFB unconnected.
• MAX1652: SECFB regulates at VSECFB = 2.50V. Tie to VL if not used.
• MAX1654: SECFB regulates at VSECFB = 0V. Tie to a negative voltage through a high-value current-
limiting resistor (I
MAX
= 100µA) if not used.
PIN
3 REF Reference Voltage Output. Bypass to GND with 0.33µF minimum.
7 FB
Feedback Input. Regulates at the feedback voltage in adjustable mode. FB is a Dual Mode
TM
input that also
selects the fixed output voltage settings as follows:
• Connect to GND for 3.3V operation.
• Connect to VL for 5V operation.
• Connect FB to a resistor divider for adjustable mode. FB can be driven with +5V CMOS logic in order to
change the output voltage under system control.
6 SHDN
Shutdown Control Input, active low. Logic threshold is set at approximately 1V (V
TH
of an internal N-channel
MOSFET). Tie SHDN to V+ for automatic start-up.
5 SYNC
Oscillator Synchronization and Frequency Select. Tie to GND or VL for 150kHz operation; tie to REF for
300kHz operation. A high-to-low transition begins a new cycle. Drive SYNC with 0 to 5V logic levels (see the
Electrical Characteristics
table for V
IH
and V
IL
specifications). SYNC capture range is 190kHz to 340kHz.
4 GND Low-Noise Analog Ground and Feedback Reference Point
12 PGND Power Ground
11 VL
5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. VL is switched to the out-
put voltage via CSL (V
CSL
> 4.5V) for automatic bootstrapping. Bypass to GND with 4.7µF. VL can supply up
to 5mA for external loads.
10 V+
Battery Voltage Input (4.5V to 30V). Bypass V+ to PGND close to the IC with a 0.1µF capacitor. Connects to a
linear regulator that powers VL.
9 CSL Current-Sense Input, low side. Also serves as the feedback input in fixed-output modes.
8 CSH Current-Sense Input, high side. Current-limit level is 100mV referred to CSL.
