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UPD1002-AI/MQ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
2014 Microchip Technology Inc. DS00001760B-page 19
UPD1002
Hub Power
Enable
HUB_PWR_EN IS This active high signal is driven by either the PCH of a
notebook or a downstream facing port (DFP) on a USB
hub. The hub or USB host may request the port to be
turned off by de-asserting this signal. Upon de-assertion,
if the device is NOT operating as a sink under a PD con-
tract, the device will de-assert the PD_EN signal to turn
off VBUS to the port, which will remain off until HUB_P-
WR_EN asserts again.
Note: In the case that the port supports insertion
detect or has a micro-AB receptacle (which
must support plug detection), the HUB_P-
WR_EN signal is ignored unless there is a
STD-A or micro-A plug inserted.
Note: This function is only available in specific
device configurations.
Port Power
Controller
Enable
PPC_PWR_EN O8 This active high signal is used to enable an attached port
power controller. It should only be used in cases in which
the only source capability offered is 5 V.
Note: In cases where the port power controller sup-
ports BC or other charging profiles, this single
signal will be enabling both power sourcing as
well as enabling the handshake emulation. BC
handshaking will occur before PD negotiation
and if in a headless/DCP charging mode, the
handshake will persist even after a PD negoti-
ation was completed successfully.
Note: This function is only available in specific
device configurations.
System Reset RESET_N IS
(PU)
System reset. This signal is active low.
Test TEST IS Test signal. This signal is used for internal purposes only
and must be connected to ground through a 1 K resistor
for normal operation.
No Connect NC - No connect. For proper operation, this signal must not be
connected.
SPI ROM Interface
SPI ROM
Clock
SPI_ROM_CLK O8 SPI clock output to the serial ROM
SPI ROM Chip
Enable
SPI_ROM_CE_N O8 This is the active low SPI ROM chip enable output. If the
SPI ROM interface is enabled, this signal should be
pulled up to the SPI ROM Vcc rail.
SPI ROM Data
In
SPI_ROM_DI IS SPI ROM data in
TABLE 2-2: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Buffer
Type
Description
UPD1002
DS00001760B-page 20 2014 Microchip Technology Inc.
SPI ROM Data
Out
SPI_ROM_DO O8
(PD)
SPI ROM data out
Note: This signal must be pulled-up to VDDIO with
an external 10 k
Ω resistor for proper opera-
tion.
Power/Ground
VTR Supply
Input
VTR P +3.3 to +5.0 V main power supply input. This signal must
be connected to a 2.2 µF capacitor to ground. Refer to
Figure 2-6 for additional power connection information.
+3.3 to +5.0 V
Variable Volt-
age I/O Power
VDDIO P +3.3 V to +5.0 V variable I/O power supply input. Refer to
Figure 2-6 for additional power connection information.
Note: When using internal +3.3 V regulator, these
pins must be externally connected to
VDD33_CAP.
+5.0 V VBUS
Input
VBUS P +5.0 V VBUS input. This signal provides power in the
dead battery case. This signal must be connected to a
2.2 µF capacitor to ground. Refer to Figure 2-6 for addi-
tional power connection information.
+1.8V Power
Delivery
PD_VDD18 P +1.8 V power for Power Delivery PHY. Refer to Figure 2-6
for additional power connection information.
Note: This pin must be connected to VDD18_CAP
pin externally when using the internal VDD18
regulator.
+1.8 V Power
Capacitance
VDD18_CAP P This pin is used to provide capacitance for the integrated
+1.8 V regulator and must be connected to a 1 µF
(<100 m
Ω ESR) capacitor to ground. Refer to Figure 2-6
for additional power connection information.
+1.8 V Analog
Power
Capacitance
VDD18A_CAP P This pin is used to provide capacitance for the integrated
+1.8 V analog regulator and must be connected to a 1 µF
(<100 m
Ω ESR) capacitor to ground. Refer to Figure 2-6
for additional power connection information.
+3.3 V Power
Capacitance
VDD33_CAP P +3.3 V regulator output. This pin must be connected to a
1µF (<100m
Ω ESR) capacitor to ground. Refer to
Figure 2-6 for additional power connection information.
Integrated
Power Switch
Capacitance
VSW_CAP P This pin is used to provide capacitance for the integrated
power switch and must be connected to a 1 µF (<100 m
Ω
ESR) capacitor to ground. Refer to Figure 2-6 for addi-
tional power connection information.
Ground VSS P Common ground. This exposed pad must be connected
to the ground plane with a via array.
TABLE 2-2: PIN DESCRIPTIONS (CONTINUED)
Name Symbol
Buffer
Type
Description
2014 Microchip Technology Inc. DS00001760B-page 21
UPD1002
2.3 Buffer Types
Note: All signals are 5 V tolerant.
TABLE 2-3: BUFFER TYPES
Buffer Type Description
IS Schmitt-triggered input
O8 Output with 8 mA sink and 8 mA source
OD8 Open-drain output with 8 mA sink
PU 50 µA (typical) internal pull-up. Unless otherwise noted in the signal description, internal
pull-ups are always enabled.
Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a
load that must be pulled high, an external resistor must be added.
PD 50 µA (typical) internal pull-down. Unless otherwise noted in the signal description, internal
pull-downs are always enabled.
Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AI Analog input
AIO Analog bi-directional
P Power pin
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

UPD1002-AI/MQ

Mfr. #:
Buy UPD1002-AI/MQ
Manufacturer:
Microchip Technology
Description:
USB Interface IC USB Power Delivery Controller 32 QFN
Lifecycle:
New from this manufacturer.
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