UPD1002
DS00001760B-page 40 2014 Microchip Technology Inc.
4.5.2 SPI ROM CONTROLLER TIMING
The following specifies the SPI ROM Controller timing requirements for the device.
4.5.3 USB POWER DELIVERY SIGNAL TIMING
All USB Power Delivery signals (PD_DATA, PD_ID) conform to the voltage, power, and timing characteristics/specifica-
tions as set forth in the USB Power Delivery Specification. Please refer to the USB Power Delivery Specification, avail-
able at http://www.usb.org.
FIGURE 4-3: SPI ROM CONTROLLER TIMING
TABLE 4-4: SPI ROM CONTROLLER TIMING VALUES
Symbol Description Min Typ Max Units
t
fc
Clock frequency 46.86 48 48.62 MHz
t
ceh
Chip enable (SPI_ROM_CE_EN) high time 50 ns
t
clq
Clock to input data 15 ns
t
dh
Input data hold time 0.70 3 4.52 ns
t
os
Output setup time 5.35 7 8.28 ns
t
oh
Output hold time 11.57 13 15.22 ns
t
ov
Clock to output valid 1.16 2 3.3 ns
t
cel
Chip enable (SPI_ROM_CE_EN) low to first clock 12 ns
t
ceh
Last clock to chip enable (SPI_ROM_CE_EN) high 12 ns
SPI_ROM_CLK
SPI_ROM_DI
SPI_ROM_DO
SPI_ROM_CE_N
t
cel
t
fc
t
clq
t
ceh
t
dh
t
oh
t
os
t
ov
t
oh
