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UPD1002-AI/MQ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
2014 Microchip Technology Inc. DS00001760B-page 31
UPD1002
Note: Only sourced currents (when the PD port is operating as a provider) can be monitored by IMON. If it is
desired to monitor a sinking current (when the port is operating as a consumer), an external circuit should
be used and the condition indicated to the device via the FAULT_IN_N pin.
3.5 SPI ROM Controller
The device is capable of code execution from an external SPI ROM. On power up, the firmware looks for an external
SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a
valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the
external SPI device. If a valid signature is not found, then execution continues from internal ROM. The following sections
describe the interface options to the external SPI ROM.
Note: Microchip suggests using the SST 25 series serial flash family, such as the SST25VF064C.
3.5.1 OPERATION OF THE HI-SPEED READ SEQUENCE
The SPI controller will automatically handle code reads going out to the SPI ROM Address. When the controller detects
a read, the controller drops the SPI_ROM_CE_N, and puts out a 0x0B, followed by the 24-bit address. The SPI controller
then puts out a DUMMY byte. The next eight clocks clock in the first byte. When the first byte is clocked in a ready signal
is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_ROM_CE_N high. As long as the addresses are sequential, the
SPI Controller will keep clocking in data.
TABLE 3-7: IMON OVERCURRENT THRESHOLDS
Negotiated Profile
Current
Overcurrent Threshold (A)
Min. Typical Max
1.5 A - 1.73 1.95
2A - 2.30 2.60
3A - 3.45 3.90
5A - 5.75 6.50
FIGURE 3-2: SPI ROM HI-SPEED READ OPERATION
SPI
CONTROLLER
SPI
ROM
Serial to
Parllel
CE#
CLK
SI
SO
UPD1002
ADDRESS
CONTROL
CACHE
SPI_ROM_DI
UPD1002
DS00001760B-page 32 2014 Microchip Technology Inc.
3.5.2 OPERATION OF THE DUAL HI-SPEED READ SEQUENCE
The SPI controller also supports dual data mode (at 30 MHz SPI speed only). When configured in dual mode, the SPI
controller will automatically handle reads going out to the SPI ROM. When the controller detects a read, the controller
drops the SPI_ROM_CE_N, and puts out a 0x3B, followed by the 24-bit address. The SPI controller then puts out a
DUMMY byte. The next four clocks clock in the first byte. The data appears two bits at a time on data out and data in.
When the first byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, the address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_ROM_CE_N high. As long as the addresses are sequential, the
SPI Controller will keep clocking in data.
FIGURE 3-3: SPI ROM HI-SPEED READ SEQUENCE
FIGURE 3-4: SPI ROM DUAL HI-SPEED READ OPERATION
SPI_ROM_CE_N
SPI_ROM_CLK
SPI_ROM_DO
SPI_ROM_DI
8
0B
MSB
HIGH IMPEDANCE
15 16
123
405
7
6
D
OUT
ADD.
23 24
ADD. ADD.
X
39 40
31
32
47 48
55 56
63 64
71 72
80
D
OUT
N
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
N+4
MSB
MSB
SPI
CONTROLLER
SPI
ROM
2-Serial to
8-Parallel
CE#
CLK
SI
SO
ADDRESS
CONTROL
CACHE
SPI_ROM_DI
UPD1002
2014 Microchip Technology Inc. DS00001760B-page 33
UPD1002
3.5.3 32-BYTE CACHE
There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once
the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential data
byte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,
the base address pointer is incremented to indicate the last 32 bytes fetched. If the device does a jump, and the jump
is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access.
3.5.4 INTERFACE OPERATION TO SPI PORT WHEN NOT PERFORMING FAST READS
There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length
register that counts out the number of bytes: SPI_CMD_LEN. Additionally, there is a self-clearing GO bit in the SPI_CTL
Register. Once the GO bit is set, the device drops SPI_ROM_CE_N, and starts clocking. It will put out SPI_CMD_LEN
X 8 number of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_ROM_DI is stored in the
SPI_RESP buffer. If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the
SPI_ROM_DO line. This mode is used for program execution out of internal RAM or ROM.
FIGURE 3-5: SPI ROM DUAL HI-SPEED READ SEQUENCE
FIGURE 3-6: SPI ROM INTERNALLY-CONTROLLED OPERATION
SPI_ROM_CE_N
SPI_ROM_CLK
SPI_ROM_DO
SPI_ROM_DI
8
0B
MSB
HIGH IMPEDANCE
15 16
123
405
7
6
D1
ADD.
23 24
ADD. ADD.
X
39 40
31
32
44
47 48
51 52
55 56
59
D2
N
N+1
D3
N+2
D4
N+3
D5
N+4
MSB
MSB
D1 D2
NN+1
D3
N+2
D4
N+3
D5
N+4
MSB
43
Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1
Bits-6,4,2,0
Bits-6,4,2,0 Bits-6,4,2,0
Bits-6,4,2,0
Bits-7,5,3,1
Bits-6,4,2,0
SPI
CONTROLLER
SPI
ROM
SPI_RSP_BUF[7:0]
SPI_CMD_BUF[3:0]
SPI_CMD_LEN
CE#
CLK
SI
SO
UPD1002
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

UPD1002-AI/MQ

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Manufacturer:
Microchip Technology
Description:
USB Interface IC USB Power Delivery Controller 32 QFN
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