NCP1582, NCP1582A, NCP1583
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7
Figure 11. Block Diagram of Gate Driver
and NonOverlap Circuitry
UVLO
FAULT
+
-
2 V
+
-
2 V
PHASE
TG
BST
V
CC
BG
GND
UVLO
FAULT
PWM
OUT
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between V
CC
and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
NCP1582, NCP1582A, NCP1583
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8
APPLICATION SECTION
Input Capacitor Selection
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
Iin
RMS
+ I
OUT
D (1 * D)
Ǹ
,
where D is the duty cycle, Iin
RMS
is the input RMS current,
& I
OUT
is the load current. The equation reaches its
maximum value with D = 0.5. Losses in the input capacitors
can be calculated with the following equation:
P
CIN
+ ESR
CIN
Iin
RMS
2
,
where P
CIN
is the power loose in the input capacitors &
ESR
CIN
is the effective series resistance of the input
capacitance. Due to large d
I
/d
t
through the input capacitors,
electrolytic or ceramics should be used. If a tantalum must
be used, it must be surge protected. Otherwise, capacitor
failure could occur.
Calculating Input Startup Current
To calculate the input start up current, the following
equation can be used.
I
inrush
+
C
OUT
V
OUT
t
SS
,
where I
inrush
is the input current during startup, C
OUT
is the
total output capacitance, V
OUT
is the desired output voltage,
and t
SS
is the soft start interval.
If the inrush current is higher than the steady state input
current during max load, then the input fuse should be rated
accordingly, if one is used.
Calculating Soft Start Time
To calculate the soft start time, the following equation can
be used.
t
SS
+
(
C
P )
C
C) * DV
I
SS
Where C
C
is the compensation as well as the soft start
capacitor,
C
P
is the additional capacitor that forms the second pole.
I
SS
is the soft start current
DV is the comp voltage from zero to until it reaches
regulation.
V
comp
V
out
1.1 V
DV
The above calculation includes the delay from comp
rising to when output voltage becomes valid.
To calculate the time of output voltage rising to when it
reaches regulation; DV is the difference between the comp
voltage reaching regulation and 1.1 V.
Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initial
drops due to the current variation inside the capacitor and the
ESR. (neglecting the effect of the effective series inductance
(ESL)):
DV
OUTESR
+ DI
OUT
ESR
COUT
,
where V
OUTESR
is the voltage deviation of V
OUT
due to the
effects of ESR and the ESR
COUT
is the total effective series
resistance of the output capacitors.
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
DV
OUTDISCHARGE
+
DI
OUT
2
L
OUT
2 C
OUT
(V
IN
D * V
OUT
)
,
where V
OUTDISCHARGE
is the voltage deviation of V
OUT
due to the effects of discharge, L
OUT
is the output inductor
value & V
IN
is the input voltage.
It should be noted that ΔV
OUTDISCHARGE
and V
OUTESR
are out of phase with each other, and the larger of these two
voltages will determine the maximum deviation of the
output voltage (neglecting the effect of the ESL).
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor value is particularly important in
spaceconstrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:
SlewRate
LOUT
+
V
IN *
V
OUT
L
OUT
.
This equation implies that larger inductor values limit the
regulators ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
NCP1582, NCP1582A, NCP1583
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9
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulators maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peaktopeak ripple
current is given by the following equation:
Ipk * pk
LOUT
+
V
OUT
(1 * D)
L
OUT
350 kHz
,
where Ipkpk
LOUT
is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as L
OUT
decreases, emphasizing the tradeoff between
dynamic response and ripple current.
Feedback and Compensation
The NCP158x allows the output of the DCDC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V
OUT
, the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
V
OUT
R1
R2
FB
The relationship between the resistor divider network
above and the output voltage is shown in the following
equation:
R
2
+ R
1
ǒ
V
REF
V
OUT
* V
REF
Ǔ
.
Resistor R1 is selected based on a design tradeoff between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
Error% +
0.1 mA R
1
V
REF
100%.
Once R1 has been determined, R2 can be calculated.
Figure 12. Type II Transconductance Error
Amplifier
R1
R2
+
V
REF
EA
Gm
R
C
C
C
C
P
Figure 12 shows a typical Type II transconductance error
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R
1
, R
2
) and external Z
FB
(R
c
, C
c
and C
p
). The
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than F
SW
/8) and the highest
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with 20 dB/decade
slope and a phase margin greater than 45°. Include
worstcase component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 13. shows the open
loop and closed loop gain plots.
Compensation Network Frequency:
The inductor and capacitor form a double pole at the
frequency
F
LC
+
1
2p @ L
O
@ C
O
Ǹ
The ESR of the output capacitor creates a “zero” at the
frequency,
F
ESR
+
1
2p @ ESR @ C
O
The zero of the compensation network is formed as,
F
Z
+
1
2p @ R
C
C
C
The pole of the compensation network is calculated as,
F
P
+
1
2p @ R
C
@ C
P

NCP1582DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers ANA BUCK CONTROLLER
Lifecycle:
New from this manufacturer.
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