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S5U13706P00C100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Page 10 Epson Research and Development
Vancouver Design Center
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
JP4 - GPO Polarity on H1
JP4 selects the polarity of the GPO signal available on LCD Connector H1.
Position 1-2 sends the GPO signal directly to H1 (default setting).
Position 2-3 inverts the GPO signal before sending it to H1.
Figure 3-3: Configuration Jumper (JP4) Location
JP6 - LCD Panel Voltage
JP6 selects the voltage level to the LCD panel.
Position 1-2 sets the voltage level to 5.0V.
Position 2-3 sets the voltage level to 3.3V (default setting).
Note
When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no
jumper and JP6 must be set to position 2-3.
Figure 3-4: Configuration Jumper (JP6) Location
JP4
Inverted
Normal
JP6
5.0V 3.3V
Epson Research and Development Page 11
Vancouver Design Center
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
4 CPU Interface
4.1 CPU Interface Pin Mapping
Note
1
A0 for these busses is not used internally by the S1D13706.
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3
These pins are not used in their corresponding Host Bus Interface mode. Systems are
responsible for externally connecting them to the host interface IO V
DD
.
Table 4-1: CPU Interface Pin Mapping
S1D13706
Pin Name
Generic #1 Generic #2
Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]
AB0 A0
1
A0 A0
1
LDS# A0 A0
1
A0
1
DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]
2
D[15:0] D[15:0]
CS# External Decode CSn# External Decode CSn# CSA#
M/R# External Decode
CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK
BS# Connected to V
DD
3
BS# AS# AS# Connected to V
DD
3
RD/WR# RD1#
Connected to
V
DD
3
RD/WR# R/W# R/W# R/W#
Connected to
V
DD
3
RD# RD0# RD# RD#
Connected to
V
DD
3
SIZ1 OE# OE#
WE0# WE0# WE# WE0#
Connected to
V
DD
3
SIZ0 EB1# LWE#
WE1# WE1# BHE# WE1# UDS# DS# EB0# UWE#
WAIT# WAIT# WAIT#
WAIT#/
RDY#
DTACK# DSACK1# N/A DTACK#
RESET# RESET# RESET# RESET# RESET# RESET# RESET# RESET#
Page 12 Epson Research and Development
Vancouver Design Center
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
4.2 CPU Bus Connector Pin Mapping
Table 4-2: CPU Bus Connector (H3) Pinout
Connector
Pin No.
Comments
1
Connected to DB0 of the S1D13706
2
Connected to DB1 of the S1D13706
3
Connected to DB2 of the S1D13706
4
Connected to DB3 of the S1D13706
5
Ground
6
Ground
7
Connected to DB4 of the S1D13706
8
Connected to DB5 of the S1D13706
9
Connected to DB6 of the S1D13706
10
Connected to DB7 of the S1D13706
11
Ground
12
Ground
13
Connected to DB8 of the S1D13706
14
Connected to DB9 of the S1D13706
15
Connected to DB10 of the S1D13706
16
Connected to DB11 of the S1D13706
17
Ground
18
Ground
19
Connected to DB12 of the S1D13706
20
Connected to DB13 of the S1D13706
21
Connected to DB14 of the S1D13706
22
Connected to DB15 of the S1D13706
23
Connected to RESET# of the S1D13706
24
Ground
25
Ground
26
Ground
27
+12 volt supply
28
+12 volt supply
29
Connected to WE0# of the S1D13706
30
Connected to WAIT# of the S1D13706
31
Connected to CS# of the S1D13706
32
Connected to MR# of the S1D13706
33
Connected to WE1# of the S1D13706
34
Connected to TXVDD1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

S5U13706P00C100

Mfr. #:
Buy S5U13706P00C100
Manufacturer:
Epson ICs
Description:
Display Development Tools S1D13706F00A Evaluation Board
Lifecycle:
New from this manufacturer.
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