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Vancouver Design Center
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
6 Technical Description
6.1 PCI Bus Support
The S1D13706 does not have on-chip PCI bus interface support. The S1D13706P00C100
uses the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13706P00C100 is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13706 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 11.
Note
The PCI Bridge FPGA must be disabled using SW1-10 in order for direct host bus inter-
faces to operate properly.
6.3 S1D13706 Embedded Memory
The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address
space is directly and contiguously available through the 17-bit address bus.
6.4 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13706 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on the buffered LCD connector (H1).
Epson Research and Development Page 17
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S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
6.5 Passive/Active LCD Panel Support
The S1D13706 directly supports:
4/8-bit single monochrome passive panels.
4/8/16-bit single color passive panels.
9/12/18-bit TFT active matrix panels.
18-bit Sharp HR-TFT panels.
18-bit Epson D-TFD panels.
All the necessary signals are provided on the 40-pin LCD connector, H1, and 16-pin
Extended LCD Connector, H2. For connection information, see Section 5, “LCD Interface
Pin Mapping” on page 14.
The S5U13706P00C100 does not provide a power supply for the LCD bias voltage needed
by passive LCD panels. An external power supply is required to provide the bias LCD
voltage to the LCD panel.
6.5.1 Buffered LCD Connector
The buffered LCD connector (H1) provides the same LCD panel signals as those directly
from S1D13706, but with voltage-adapting buffers selectable to 3.3V or 5.0V. Pin 32 on
this connector provides a voltage level of 3.3V or 5.0V to the LCD panel logic (see “JP6 -
LCD Panel Voltage” on page 10 for information on setting the panel voltage).
6.5.2 Extended LCD Connector
The S1D13706 directly supports Sharp 18-bit HR-TFT and Epson 18-bit D-TFD panels.
The extended LCD connector (H2) provides the extra signals required to support these
panels. The signals on this connector are also buffered from the S1D13706 and adjustable
to 3.3V or 5.0V (see “JP6 - LCD Panel Voltage” on page 10 for details on setting the panel
voltage).
6.6 External oscillator support for CLKI and CLKI2
The S1D13706 uses CLKI and CLKI2 signals provided by two +5V oscillators. The oscil-
lators are mounted on the evaluation board in 14-pin DIP sockets. The 5V clock signals are
shifted to 3.3V which is accepted by the S1D13706.
Page 18 Epson Research and Development
Vancouver Design Center
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
7 References
7.1 Documents
Epson Research and Development, Inc., S1D13706 Hardware Functional Specification,
document number X31B-A-001-xx.
Epson Research and Development, Inc., S1D13706 Programming Notes and Examples,
document number X31B-G-003-xx.
7.2 Document Sources
Epson Research and Development: http://www.erd.epson.com.

S5U13706P00C100

Mfr. #:
Manufacturer:
Epson ICs
Description:
Display Development Tools S1D13706F00A Evaluation Board
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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