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S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
The S1D13706 has 8 configuration inputs (CNF[7:0]) which are read on the rising edge of
RESET#. All S1D13706 configuration inputs are fully configurable using a ten position
DIP switch as described below.
1
To enable the Hardware Video Invert function the following are required:
• GPIO pins must be enabled (S1-4 closed).
• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1b.
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0b.
• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1b.
Table 3-1: Configuration DIP Switch Settings
Switch
S1D13706
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
SW1-[3:1] CNF[2:0]
Select host bus interface as follows:
CNF2 CNF1 CNF0 Host Bus Interface
000 SH-4/SH-3
0 0 1 MC68K #1
0 1 0 MC68K #2
0 1 1 Generic #1
1 0 0 Generic #2
101 RedCap 2
1 1 0 DragonBall
111 Reserved
Note: The host bus interface is 16-bit.
SW1-4 CNF3 Enable GPIO pins Enable additional pins for D-TFD/HR-TFT
SW1-5 CNF4 Big Endian bus interface
Little Endian bus interface
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-[8:7] CNF[7:6]
CLKI to BClk divide select:
CNF7 CNF6 CLKI to BClk Divide Ratio
00 1 : 1
01 2 : 1
10 3 : 1
11 4 : 1
SW1-9
1
- Hardware Video Invert - invert video data
1
Hardware Video Invert - normal video data
1
SW1-10 - Disable FPGA for non-PCI host Enable FPGA for PCI host
= Required settings when used with PCI Bridge FPGA
