AD5308/AD5318/AD5328
Rev. F | Page 11 of 28
02812-018
I
DD
(mA)
SUPPLY VOLTAGE (V)
1.3
0.6
0.7
0.9
1.0
2.0
1.2
1.1
0.8
2.5 3.0 3.5 4.0 4.5 5.0
T
A
= 25°C
V
REF
= V
DD
V
REF
= 2V, GAIN = +1,
BUFFERED
V
REF
= 2V, GAIN = +1, UNBUFFERED
V
REF
= V
DD
, GAIN = +1, UNBUFFERED
Figure 16. Supply Current vs. Supply Voltage
02812-019
V
DD
(V)
I
DD
POWER-DOWN (
μ
A)
1.0
0
0.8
0.2
0.4
0.6
2.0
0.9
0.7
0.1
0.3
0.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
T
A
= 25°C
Figure 17. Power-Down Current vs. Supply Voltage
02812-020
V
LOGIC
(V)
I
DD
(mA)
0.6
0 1.0
0.7
0.8
1.0
1.2
1.4
2.0 3.0 4.0
DECREASING
V
DD
= 3V
INCREASING
0.9
1.1
1.3
1.5 2.5 3.50.5 4.5 5.0
T
A
= 25°C
V
DD
= 5V
Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing
and Decreasing
02812-021
CH1
CH2
V
OUT
A
SCLK
CH1 1V, CH2 5V, TIME BASE = 1μs/DIV
T
A
= 25°C
V
DD
= 5V
V
REF
= 5V
Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
02812-022
H1
H2
CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV
V
OUT
A
V
DD
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
Figure 20. Power-On Reset to 0 V
02812-023
CH1
CH2
V
OUT
A
CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV
PD
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
Figure 21. Exiting Power-Down to Midscale
