AD5308/AD5318/AD5328
Rev. F | Page 19 of 28
MICROPROCESSOR INTERFACE
ADSP-2101/ADSP-2103-to-
AD5308/AD5318/AD5328 INTERFACE
Figure 36 shows a serial interface between the AD5308/AD5318/
AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low framing,
and 16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled. The data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5308/AD5318/ AD5328 on the falling edge
of the DACs SCLK.
02812-036
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
AD5308/
AD5318/
AD5328*
SYNC
DT
SCLK SCLK
DIN
Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface
68HC11/68L11-to-AD5308/AD5318/AD5328
INTERFACE
Figure 37 shows a serial interface between the AD5308/AD5318/
AD5328 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328,
and the MOSI output drives the serial data line (DIN) of the DAC.
The sync signal is derived from a port line (PC7). The set up
conditions for the correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit is a
0 and its CPHA bit is a 1. When data is being transmitted to the
DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11
is configured as just described, data appearing on the MOSI output
is valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5308/AD5318/AD5328, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
02812-037
68HC11/68L11
*ADDITIONAL PINS OMITTED FOR CLARITY
PC7
AD5308/
AD5318/
AD5328*
SYNC
MOSI
SCK
DIN
SCLK
Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface
80C51/80L51-to-AD5308/AD5318/AD5328
INTERFACE
Figure 38 shows a serial interface between the AD5308/AD5318/
AD5328 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5308/AD5318/AD5328, while RxD drives the serial data
line of the part. The
SYNC
signal is again derived from a bit
programmable pin on the port. In this case, port line P3.3 is used.
When data is transmitted to the AD5308/AD5318/AD5328, P3.3
is taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a format
that has the LSB first. The AD5308/AD5318/AD5328 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
02812-038
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
AD5308/
AD5318/
AD5328*
SYNC
RxD
TxD
DIN
SCLK
Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface
AD5308/AD5318/AD5328
Rev. F | Page 20 of 28
MICROWIRE-to-AD5308/AD5318/AD5328
INTERFACE
Figure 39 shows an interface between the AD5308/AD5318/
AD5328 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5308/AD5318/AD5328 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
02812-039
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
AD5308/
AD5318/
AD5328*
SYNC
SO
SK
DIN
SCLK
Figure 39. MICROWIRE-to-AD5308/AD5318/AD5328 Interface
AD5308/AD5318/AD5328
Rev. F | Page 21 of 28
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
The AD5308/AD5318/AD5328 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0.25 V to V
DD
.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780, ADR381, and REF192 (2.5 V references). For 2.5 V
operation, a suitable external reference is the AD589 or the
AD1580 (1.2 V band gap references). Figure 40 shows a typical
setup for the AD5308/AD5318/AD5328 when using an external
reference.
02812-040
AD5308/AD5318/
AD5328
GND
DIN
SYNC
SERIAL
INTERFACE
V
OUT
EXT
REF
0.1μF
V
REF
ABCD
V
REF
EFGH
A
D780/ADR3811/REF192
W
ITH V
DD
= 5V OR
A
D589/AD1580 WITH
V
DD
= 2.5V
V
DD
= 2.5V TO 5.5V
V
IN
10μF
1μF
SCL
V
OUT
A
V
OUT
G
V
OUT
B
V
OUT
H
Figure 40. AD5308/AD5318/AD5328 Using a 2.5 V or 5 V External Reference
DRIVING V
DD
FROM THE REFERENCE VOLTAGE
If an output range of 0 V to V
DD
is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference input to V
DD
. As this supply can be noisy
and not very accurate, the AD5308/AD5318/AD5328 can be
powered from a voltage reference. For example, using a 5 V
reference, such as the REF195, works because the REF195
outputs a steady supply voltage for the AD5308/AD5318/
AD5328. The typical current required from the REF195 is a
1 A supply current and ≈ 112 A into the reference inputs (if
unbuffered); this is with no load on the DAC outputs. When the
DAC outputs are loaded, the REF195 also needs to supply the
current to the loads. The total current required (with a10 k
load on each output) is
1.22 mA + 8(5 V/10 k) = 5.22 mA
The load regulation of the REF195 is typically 2.0 ppm/mA,
which results in an error of 10.4 ppm (52 V) for the 5.22 mA
current drawn from it. This corresponds to a 0.003 LSB error at
8 bits and 0.043 LSB error at 12 bits.
BIPOLAR OPERATION USING THE
AD5308/AD5318/AD5328
The AD5308/AD5318/AD5328 have been designed for single-
supply operation, but a bipolar output range is also possible
using the circuit in Figure 41. This circuit gives an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820, the AD8519, or an OP196
as the output amplifier.
02812-041
+5V
–5V
AD820/
AD8519/
OP196
10μF
+6V TO +16V
0.1μF
R1
10kΩ
±5V
R2
10kΩ
GND
GND
V
OUT
REF192
+5V
SERIAL
INTERFACE
SCLK
SYNC
DIN
1
μ
F
AD5308/
AD5318/
AD5328
V
REF
ABCD
V
REF
B
V
OUT
C
V
OUT
B
V
OUT
A
V
OUT
H
V
IN
V
DD
Figure 41. Bipolar Operation with the AD5308/AD5318/AD5328
The output voltage for any input code can be calculated as
follows:
()
()
R1RREFIN
R1
RR1DREFIN
V
N
OUT
/2
22/
×
+××
=
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
with
REFIN = 5 V , R1 = R2 = 10 k
(
)
VDV
N
OUT
52/10 ×=
OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
The AD5308/AD5318/AD5328 have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise and
safety requirements, or distance, it may be necessary to isolate
the AD5308/AD5318/AD5328 from the controller. This can
easily be achieved by using opto-isolators that provide isolation
in excess of 3 kV. The actual data rate achieved may be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5308/AD5318/AD5328 makes them ideally suited for
use in opto-isolated applications. Figure 42 shows an opto-
isolated interface to the AD5308/AD5318/AD5328 where DIN,
SCLK, and
SYNC
are driven from optocouplers. The power
supply to the part also needs to be isolated. This is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5308/
AD5318/AD5328.

AD5318ARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC OCTAL 10 BIT SPI MICROPWR IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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