FIDO5100BBCZ

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

Data Sheet fido5100/fido5200

Rev. 0 | Page 13 of 19

Data Bus Width

The host interface supports either a 16-bit or 32-bit wide data

bus. The data bus width is determined by the SIZE_32 (Pin E3)

signal that is sampled on the rising edge of

RESET

. See Table 5

for pin function descriptions for the SIZE_32 and

RESET

signals.

Endianness

The host interface presents data on the data bus in either big

endian or little endian format. The endianness of the data is

determined by the LE signal (Pin E2), which is sampled on the

rising edge of the

RESET

signal. See Table 5 for pin function

descriptions for the LE and

RESET

signals.

The REM switch data bus is defined as follows:

• D0 = LSB

• D15 = MSB for 16-bit bus

• D31 = MSB for 32-bit bus

For all control/status register accesses, there is no difference in

operation based on the setting of the LE pin. The data

representation in a host processor register must match the data

that is transferred over the bus.

All control/status registers are 16-bits wide. If using a 32-bit

bus, transfer the data in the following order: D15 to D0 (D31 to

D16 are ignored when using a 32-bit bus). For example, the

REM switch driver reads the device number register early in the

initialization process. In the case of the number, 0x00003300, the

value read from this register must be transferred across the bus,

as shown in Table 6. When evaluated in the software on the host

processor, the value of these 32 bits results in 0x00003300.

For queue accesses, the REM switch treats all data as byte

arrays. Consider the following example of a stream of bytes

received over an Ethernet cable into a REM switch port and

then transferred to the host. The packet data in network order is

as follows: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,

0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F.

The data is read differently depending on the setting, as follows:

• Big endian 16-bit host interface: 0x0001, 0x0203, 0x0405,

0x0607, 0x0809, 0x0A0B, 0x0C0D, 0x0E0F.

• Big endian 32-bit host interface: 0x00010203, 0x04050607,

0x08090A0B, 0x0C0D0E0F.

• Little endian 16-bit host interface: 0x0100, 0x0302, 0x0504,

0x0706, 0x0908, 0x0B0A, 0x0D0C, 0x0F0E.

• Little endian 32-bit host interface: 0x03020100,

0x07060504, 0x0B0A0908, 0x0F0E0D0C.

Consult the REM Switch Software Driver User Guide, available

at www.analog.com/en/products/industrial-ethernet.html for

more details on how to handle endianness in an application of

a device.

Table 6. Control/Status Registers Bit Map

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0

Table 7. Big Endian 16-Bit Data Bus Bit Map, 0x0E0F Hexadecimal

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1

Table 8. Big Endian 32-Bit Data Bus Bit Map, 0x0C0D0E0F Hexadecimal

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1

Table 9. Little Endian 16-Bit Data Bus Bit Map, 0x0E0F Hexadecimal

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0

Table 10. Little Endian 32-Bit Data Bus Bit Map, 0x0F0E0D0C Hexadecimal

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0

fido5100/fido5200 Data Sheet

Rev. 0 | Page 14 of 19

Address/Data Bus Operation

The host interface address/data bus connects to the address/

data bus of the CPU. There are four bits of data for the address

bus and either 16 bits or 32 bits of data for the data bus. Each

REM switch address is 32-bit aligned, meaning that the addresses

increment by four bytes (A05 to A02). Regardless of whether the

data bus is 16 bits wide or 32 bits wide, the least significant

address bit supplied to the REM switch is always the same.

In addition, all accesses to indirect registers return the register

data in the lower 16 bits only (even if the interface is 32 bits

wide). For wider registers, such as a 64-bit timer, use a repeated

set of reads or writes to access the full content of the register.

Nonmultiplexed Address Data Bus

MBS = 0 selects the nonmultiplexed address data bus configura-

tion. The read and write cycle timings are defined in Figure 2

and Figure 3. See Table 2 for the read and write cycle timing

parameters.

Multiplexed Address Data Bus

MBS = 1 selects the multiplexed address data bus configuration.

The read and write cycle timings are defined in Figure 4 and

Figure 5. See Table 3 for the read and write cycle timing

parameters.

Register and Data Access

Four bits of address provide direct access to 16 registers. A read

cycle or a write cycle obtains or sets the data in these registers.

To a ccess additional registers, use the host indirect address

register. The direct address register definitions are provided in

Table 11.

The REM switch software driver provides the necessary application

programming interface (API) functions to access these registers

and manage all aspects of the switch for a specific protocol. Ether-

net packets are received and transmitted directly through the

Queue 0, Queue 1, Queue 2, and Queue 3 read and write registers,

depending on the protocol.

Ethernet protocol control and switch management are

performed by the software driver API through the host

read/write queue data registers and the host direct/indirect

registers (refer to the REM Switch Driver User Guide, available

at www.analog.com/en/products/industrial-ethernet.html, for

more information about these registers). Interrupt management

is performed by the software driver API using the three

interrupt lines in conjunction with the queue status register,

timer status register, universal input/output controller (UIC)

interrupt status register, and the composite interrupt status

register.

Table 11. Direct Address Register Definitions

Register Name

Width

Address[5:0]

Read/Write

1

Reset Value

2

Queue 0 Read 16/32 0x00 R 0x00000000

Queue 0 Write

16/32

0x00

W

N/A

Queue 1 Read 16/32 0x04 R 0x00000000

Queue 1 Write 16/32 0x04 W N/A

Queue 2 Read 16/32 0x08 R 0x00000000

Queue 2 Write 16/32 0x08 W N/A

Queue 3 Read 16/32 0x0C R 0x00000000

Queue 3 Write

16/32

0x0C

W

N/A

Reserved N/A 0x10 to 0x14 N/A

Host Read Queue 0 Data 16/32 0x18 R 0x00000000

Host Read Queue 0 Data Head 16/32 0x18 W 0x00000000

Host Read Queue 1 Data 16/32 0x1C R 0x00000000

Host Read Queue 1 Data Head 16/32 0x1C W N/A

Queue Status Register 16 0x20 R/W 0x00000F00

Timer Status Register 16 0x24 R/W 0x00000000

UIC Interrupt Status 16 0x28 R/W 0x0000

Composite Interrupt Status 16 0x2C R 0x0000

Host Indirect Address 16 0x30 R/W 0x0000

Host Indirect Read Data

16

0x34

R

N/A

Host Indirect Write Data 16 0x34 W N/A

Host Write Queue 0 Completion 16 0x38 R 0x0000

Host Write Queue 1 Completion 16 0x3C R 0x0000

1

R means read only, W means write only, and R/W means read/write.

2

N/A means not applicable.

Data Sheet fido5100/fido5200

Rev. 0 | Page 15 of 19

Interrupts

Three interrupt lines are outputs from the REM switch; these

three lines are labeled INT0, INT1, and INT2. Each of these

interrupt lines must be mapped according to the interrupt

inputs of the host processor. To ensure the best protocol

performance, give INT2 the highest priority in the processor

priority scheme, and do not disable it.

The interrupt lines are mapped to the events defined by the

queue status register, timer status register, UIC interrupt status

register, and composite interrupt status register for each protocol.

It is the responsibility of the software driver API to provide the

appropriate interrupt service routine for the mapped event.

Refer to the REM Switch Driver User Guide, available at

www.analog.com/en/products/industrial-ethernet.html, for

technical details on handling REM switch interrupts for a

specific industrial Ethernet protocol.

When an interrupt event defined in the appropriate status

registers occurs, the associated REM switch interrupt output

line becomes active (Logic 1) and remains active until the

register is cleared. If multiple events are mapped to the same

REM switch interrupt output, and more than one becomes

active, the associated interrupt line remains in the active (Logic 1)

state until all active interrupt source registers are cleared.

Note that although the interrupts, INT0, INT1, and INT2, are

labeled as priorities of low, medium, and high, there is not any

inherent priority on the lines themselves, and they can be mapped

accordingly.

ETHERNET INTERFACE

There are two Ethernet ports on the REM switch. Each port is

capable of configuration to support RMII or MII. Each port also

has an input for link status from the PHY and an output for a

link activity LED.

Connections

The pins associated specifically with the RMII and MII

interfaces are listed in Table 12; their full descriptions are

defined in Table 5.

The RMII interface is a seven-signal interface for each port (see

Figure 9). This interface uses a 50 MHz reference clock

(RMII_CLK) provided by the REM switch to the PHY.

The MII interface is a 14-signal interface for each port (see

Figure 10). The REM switch provides the base clock to the

PHYs using the synchronized 25 MHz CLKOUT signal. The

PHYs then provide a receive and transmit clock (RX_CLK and

TX_CLK) for each port.

Link Status and Activity

The

Px_LINK_STATUS

signal is an input to the REM switch

from the selected PHY, configured so that the

Px_LINK_STATUS

signal is asserted continuously (not blinking) and determines

the link up or link down state.

The

Px_ACTIVITY

signal is an output from the REM switch

and is typically used to drive an LED to indicate a link is valid.

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FIDO5100BBCZ

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Ethernet ICs REM Switch

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