Data Sheet fido5100/fido5200
Rev. 0 | Page 5 of 19
TIMING SPECIFICATIONS—MULTIPLEXED ADDRESS DATA BUS
Table 3. Multiplexed Address Data Bus—Read and Write Cycle Timing
1
Parameter Min Typ Max Unit Description
ALEH
t
ALEL
16 ns ALE low time
t
AS
170 ps Address setup time
t
AH
170 ps Address hold time
t
CDV
20 ns ALE to valid data
t
ALOE
2 ns ALE to output enable
t
ODV
20 ns Output enable to data valid
t
DHZ
150 ps Output disable to high-Z time
t
CHZ
150 ps
CS high to high-Z time
t
CLLL
0 ns
CS low to ALE low
t
CSH
8 ns
CS high time
t
EOE
2 ns
CS to output enable
t
DO
2 110 ps Output enable to output drive time
t
COE
0 ns
Output disable to
CS high
t
WES
0 ns
CS to write enable
t
WEWC
16 ns Write enable to write complete
t
WECS
0 ns
Write enable high to
CS high
WHLH
WE high to next ALE high
t
DS
60 ps
Data setup to
WE high
t
DH
60 ps
Input data hold after
WE high
1
The MBS pin determines whether the host interfaced has multiplexed or separate address and data lines. When MBS = 1, the interface is multiplexed.
Timing Diagrams Multiplexed REM Switch
ADDRESS
ADDRESS
BUS
ALE
DATA OUT
t
AS
t
AH
t
ALEH
t
ALOE
t
DO
t
DHZ
t
CHZ
t
COE
t
CLLL
t
CDV
t
ALEL
OE
CS
t
CSH
t
ODV
t
EOE
15833-004
Figure 4. REM Switch Multiplexed Address and Data Bus Read Timing, MBS = 1
