PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 13 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.2 Application examples including switches to battery
9. Limiting values
[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 5 “
Static characteristics. See Section 7.4 for series resistor requirements.
Fig 10. Clamp 15 (ignition) detection Fig 11. Switches to battery and ground with
cyclic biasing
002aae030
IN0
PCA9703
IN1
IN15
switch bias
clamp 15
002aae031
IN0
PCA9703
IN1
IN15
switch bias
BAT BAT
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
T
amb
=
40
Cto+125
C, unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6.0 V
I
I
input current IN[15:0] pins with series resistor and
V
I
>5.5V
[1]
- 350 A
V
I
input voltage GPI pins IN[15:0]; no series resistor
[1]
0.5 +6 V
SPI pins 0.5 +6 V
T
stg
storage temperature 65 +150 C
T
j(max)
maximum junction temperature operating - 125 C
PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 14 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
10. Static characteristics
[1] V
DD
must be lowered to 0.2 V for at least 5 s in order to reset device.
[2] Minimum V
IL
is 2.5 V at V
DD
=4.5V.
[3] For GPI pin voltages > 5.5 V, see Section 7.4
.
Table 5. Static characteristics
V
DD
= 4.5 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +125
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
DD
supply voltage 4.5 5.0 5.5 V
I
DD
supply current V
DD
=5.5V; input=5Vor18V;
INT_EN = V
DD
-1.02.5A
V
POR
power-on reset voltage
[1]
-1.82.2V
General Purpose Inputs (IN0 to IN15)
V
IL
LOW-level input voltage
[2]
- - 0.55V
DD
V
V
IH
HIGH-level input voltage 0.8V
DD
-- V
V
hys
hysteresis voltage V
DD
= 4.5 V - 70 - mV
I
I
input current GPI recommended maximum current;
V
I
> 5.5 V; with series resistor R
s
[3]
- - 100 A
I
IH
HIGH-level input current each input; V
I
=V
DD
1-+1A
I
LI
input leakage current V
I
= 17 V; 100 k series resistor 1-+1A
C
i
input capacitance V
I
=V
SS
or V
DD
-2.05.0pF
Interrupt output (INT
)
I
OL
LOW-level output current V
DD
=4.5V; V
OL
=0.4V 6 - - mA
I
OH
HIGH-level output current V
OH
=V
DD
1-+1A
C
o
output capacitance - 2 5 pF
SPI and control (SDOUT, SDIN, SCLK, CS
, INT_EN)
V
IL
LOW-level input voltage - - 0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
IH
HIGH-level input current SDIN; V
I
=V
DD
= 5.5 V - 20 40 A
I
OL
LOW-level output current SDOUT; V
OL
=0.4V; V
DD
=4.5V 5 - - mA
I
OH
HIGH-level output current SDOUT; V
OH
=V
DD
0.5 V; V
DD
=4.5V 5 11 - mA
C
i
input capacitance V
I
=V
SS
or V
DD
-25pF
C
o
output capacitance SDOUT; CS =V
DD
-46pF
PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 15 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
11. Dynamic characteristics
Table 6. Dynamic characteristics
V
DD
= 4.5 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +125
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
max
maximum input clock frequency - - 5 MHz
t
r
rise time SDOUT; 10 % to 90 % at 5 V - 35 60 ns
t
f
fall time SDOUT; 90 % to 10 % at 5 V - 25 50 ns
t
WH
pulse width HIGH SCLK 50 - - ns
t
WL
pulse width LOW SCLK 50 - - ns
t
SPILEAD
SPI enable lead time CS falling edge to SCLK rising edge 50 - - ns
t
SPILAG
SPI enable lag time SCLK falling edge to CS rising edge 50 - - ns
t
su(SDIN)
SDIN set-up time SDIN to SCLK falling edge 20 - - ns
t
h(SDIN)
SDIN hold time from SCLK falling edge 30 - - ns
t
en(SDOUT)
SDOUT enable time from CS LOW to
SDOUT low-impedance; Figure 15
--55ns
t
dis(SDOUT)
SDOUT disable time from rising edge of CS to SDOUT
high-impedance; Figure 15
--85ns
t
v(SDOUT)
SDOUT valid time from rising edge of SCLK; Figure 16 --55ns
t
su(SCLK)
SCLK set-up time SCLK falling to CS falling 50 - - ns
t
h(SCLK)
SCLK hold time SCLK rising after CS rising 50 - - ns
t
POR
power-on reset pulse time time before CS is active
after V
DD
>V
POR
- - 250 ns
t
rel(int)
interrupt release time after CS going LOW; Figure 17 - - 500 ns
t
v(INT)
valid time on pin INT after INn changes or INT_EN
goes HIGH
- 200 800 ns
Fig 12. Timing diagram
CS
SCLK
SDIN
SDOUT
INT
t
SPILAG
t
WL
t
WH
high-impedance
t
SPILEAD
MSB in
MSB out
002aac428
t
su(SDIN)
t
h(SDIN)
t
en(SDOUT)
t
v(SDOUT)
t
dis(SDOUT)
t
rel(int)
50 % 50 %
t
su(SCLK)
t
h(SCLK)

PCA9703PW/Q900,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized 16B 3V THRES SPI 18V GPI INT - 40 +125
Lifecycle:
New from this manufacturer.
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