PCA9703 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 5 September 2014 8 of 28
NXP Semiconductors
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
register. The interrupt mask bit pattern must be positioned into the shift register prior to the
CS
rising edge. Misaligned mask pattern will result in unexpected activation of the
interrupt signal.
The interrupt output is asserted when the input status is changed, and the interrupt mask
bit corresponding to the input pin that caused the change is unmasked (bit value = 1), and
is cleared on the falling edge of CS
or when the input port status matches the input status
register. When there are multiple devices, the INT
outputs may be tied together to a single
pull-up.
Table 3
illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
[1] Input status register is the value or content of the D flip-flops.
[2] Logic states shown for INT
pin assumes 10 k pull-up resistor.
7.3 Interrupt enable
INT_EN is the interrupt output enable input and the general purpose input enable input. It
is an active HIGH input. When the INT_EN pin is LOW the GPI pins are turned off and the
input state is saved to minimize power loss when the input pull-ups or pull-downs are
cycled and the INT
output is disabled. The cycled pull-ups or pull-downs should be active
sufficiently long before the INT_EN is taken active that the GPI pin voltage is completely
settled to prevent false or transient interrupt signals.
7.4 General Purpose Inputs
The General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part when the input voltage is above 5.5 V.
Table 3. Interrupt output function truth table
H = HIGH; L = LOW; X = don’t care
INT_EN Input port status Input status register
[1]
INT output
[2]
Mask bit = 1
(unmasked)
Mask bit = 0
(masked)
HL L H H
HL H L H
HH L L H
HH H H H
LX X H H
