SCANPSC110FSC Datasheet SCANPSC110FSC, SCANPSC110FSCX | P10-P12

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SCANPSC110F

Level 1 Protocol (Continued)

FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register

FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register

Level 2 Protocol

Once the SCANPSC110F Bridge has been successfully

addressed and selected, its internal registers may be

accessed via Level-2 Protocol. Level-2 Protocol is compli-

ant to IEEE Std. 1149.1 TAP protocol with one exception: if

the SCANPSC110F is selected via the Broadcast or Multi-

Cast address, TDO

will always be 3-STATED. (The TDO

buffer must be implemented this way to prevent bus con-

tention.)

Upon being selected, (i.e., the SCANPSC110F Selection

controller transitions from the Wait-For-Address state to

one of the Selected states), each of the local scan ports

(LSP

, LSP

) remains parked in one of the following

four TAP Controller states: Test-Logic-Reset, Run-Test/

Idle, Pause-DR, or Pause-IR and the active scan chain will

consist of: TDI

through the instruction register (or the

IDCODE register) and out through TDO

TDI

→Instruction Register→TDO

The UNPARK instruction (described later) is used to insert

one or more local scan ports into the active scan chain.

Table 4 describes which local ports are inserted into the

chain, and in what order.

LEVEL 2 INSTRUCTION TYPES

There are two types of instructions (reference Table 5):

1. Instructions that insert a SCANPSC110F register into

the active scan chain so that the register can be cap-

tured or updated (BYPASS, SAMPLE/PRELOAD,

EXTEST, IDCODE, MODESEL, MCGRSEL, LFSR-

SEL, CNTRSEL).

2. Instructions that configure local ports or control the

operation of the linear feedback shift register and

counter registers (UNPARK, PARKTRL, PARKRTI,

PARKPAUSE, GOTOWAIT, SOFTRESET, LFSRON,

LFSROFF, CNTRON, CNTROFF). These instructions,

11 www.fairchildsemi.com

SCANPSC110F

Level 2 Protocol (Continued)

along with any other yet undefined Op-Codes, will

cause the device identification register to be inserted

into the active scan chain.

LEVEL 2 INSTRUCTION DESCRIPTIONS

BYPASS: The BYPASS instruction selects the bypass reg-

ister for insertion into the active scan chain when the

SCANPSC110F is selected.

EXTEST: The EXTEST instruction selects the boundary-

scan register for insertion into the active scan chain. The

boundary-scan register consists of seven “sample only”

shift cells connected to the S

(0–5)

and OE inputs. On the

SCANPSC110F, the EXTEST instruction performs the

same function as the SAMPLE/PRELOAD instruction,

since there aren’t any scannable outputs on the device.

SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruc-

tion selects the boundary-scan register for insertion into the

active scan chain. The boundary-scan register consists of

seven “sample only” shift cells connected to the S

(0–5)

and

inputs.

IDCODE: The IDCODE instruction selects the device iden-

tification register for insertion into the active scan chain.

When IDCODE is the current active instruction the device

identification “0FC0E01F” Hex is captured upon exiting the

Capture-DR state.

TABLE 5. Level 2 Protocol and Op-Codes

Note 4: All other instructions act on selected SCANPSC110Fs only.

UNPARK: This instruction unparks the Local Scan Port

Network and inserts it into the active scan chain as config-

ured by the Mode register (see Table 4). Unparked LSPs

are sequenced synchronously with the SCANPSC110F's

TAP controller.

When a LSP has been parked in the Test-Logic-Reset or

Run-Test/Idle state, it will not become unparked until the

SCANPSC110F's TAP Controller enters the Run-Test/Idle

state following the UNPARK instruction. If an LSP has been

parked in one of the stable pause states (Pause-DR or

Pause-IR), it will not become unparked until the

SCANPSC110F's TAP Controller enters the respective

pause state. (See Figures 9, 10, 11, 12).

PARKTLR: This instruction causes all unparked LSPs to

be parked in the Test-Logic-Reset TAP controller state and

removes the LSP network from the active scan chain. The

LSP controllers keep the LSPs parked in the Test-Logic-

Reset state by forcing their respective TMS

output with a

constant logic “1” while the LSP controller is in the Parked-

TLR state (see Figure 4).

PARKRTI: This instruction causes all unparked LSPs to be

parked in the Run-Test/Idle state. When a LSP

is active

(unparked), its TMS

signals follow TMS

and the LSP

controller state transitions are synchronized with the TAP

Controller state transitions of the SCANPSC110F. When

the instruction register is updated with the PARKRTI

instruction, TMS

will be forced to a constant logic “0”,

causing the unparked local TAP Controllers to be parked in

the Run-Test/Idle state. When an LSP

is parked, it is

removed from the active scan chain.

PARKPAUSE: The PARKPAUSE instruction has dual func-

tionality. It can be used to park unparked LSPs or to unpark

parked LSPs. The instruction places all unparked LSPs in

one of the TAP Controller pause states. A local port does

not become parked until the SCANPSC110F's TAP Con-

troller is sequenced through Exit1-DR/IR into the Update-

DR/IR state. When the SCANPSC110F TAP Controller is in

the Exit1-DR or Exit1-IR state and TMS

is HIGH, the LSP

controller forces a constant logic '0” onto TMS

thereby

parking the port in the Pause-DR or Pause-IR state respec-

tively (see Figure 4 ). Another instruction can then be

loaded to reconfigure the local ports or to deselect the

SCANPSC110F (i.e., MODESEL, GOTOWAIT, etc.).

Instructions Hex Op-Code Binary Op-Code Data Register

BYPASS FF 11111111 Bypass Register

EXTEST 00 00000000 Boundary-Scan Register

SAMPLE/PRELOAD 81 10000001 Boundary-Scan Register

IDCODE AA 10101010 Device Identification Register

UNPARK E7 11100111 Device Identification Register

PARKTLR C5 11000101 Device Identification Register

PARKRTI 84 10000100 Device Identification Register

PARKPAUSE C6 11000110 Device Identification Register

GOTOWAIT* C3 11000011 Device Identification Register

MODESEL 8E 10001110 Mode Register

MCGRSEL 03 00000011 Multi-Cast Group Register

SOFTRESET 88 10001000 Device Identification Register

LFSRSEL C9 11001001 Linear Feedback Shift Register

LFSRON 0C 00001100 Device Identification Register

LFSROFF 8D 10001101 Device Identification Register

CNTRSEL CE 11001110 32-Bit TCK Counter Register

CNTRON 0F 00001111 Device Identification Register

CNTROFF 90 10010000 Device Identification Register

Other Undefined TBD TBD Device Identification Register

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SCANPSC110F

Level 2 Protocol (Continued)

If the PARKPAUSE instruction is given to a bridge whose

LSPs are parked in Pause-IR or Pause-DR, the parked

LSPs will become unparked when the SCANPSC110F’s

TAP controller is sequenced into the respective Pause

state.

The PARKPAUSE instruction was implemented with this

dual functionality to enable backplane testing (interconnect

testing between boards) with simultaneous Updates and

Captures.

Simultaneous Update and Capture of several boards can

be performed by parking LSPs of the different boards in the

Pause-DR TAP controller state, after shifting the data to be

updated into the boundary registers of the components on

each board. The broadcast address is used to select all

SCANPSC110Fs connected to the backplane. The PARK-

PAUSE instruction is scanned into the selected

SCANPSC110Fs and the SCANPSC110F TAP controllers

are sequenced to the Pause-DR state where the LSPs of

all SCANPSC110Fs become unparked. The local TAP con-

trollers are then sequenced through the Update-DR,

Select-DR, Capture-DR, Exit1-DR, and parked in the

Pause-DR state, as the SCANPSC110F TAP controller is

sequenced into the Update-DR state. When a LSP is

parked, it is removed from the active scan chain.

GOTOWAIT: This instruction is used to return all

SCANPSC110Fs to the Wait-For-Address state. All

unparked LSPs will be parked in the Test-Logic-Reset TAP

controller state (see Figure 5).

MODESEL: The MODESEL instruction inserts the mode

determines the LSPN configuration. Bit 7 of the mode reg-

ister is a read-only counter status flag.

MCGRSEL: This instruction inserts the multi-cast group

used to group SCANPSC110Fs into multi-cast groups for

parallel TAP sequencing (i.e., to simultaneously perform

identical scan operations).

SOFTRESET: This instruction causes all 3 Port configura-

tion controllers (Figure 4) to enter the Parked-TLR state,

which forces TMS

HIGH; this parks each local port in the

Test-Logic-Reset state within 5 TCK

cycles.

LFSRSEL: This instruction inserts the linear feedback shift

pacted signature to be shifted out of the LFSR during the

Shift-DR state. (The signature is assumed to have been

computed during earlier LFSRON shift operations.) This

instruction disables the LFSR register’s feedback circuitry,

turning the LFSR into a standard 16-bit shift register. This

allows a signature to be shifted out of the register, or a

seed value to be shifted into it.

LFSRON: Once this instruction is executed, the linear

feedback shift register samples data from the active scan

path (including all unparked TDI

) during the Shift-DR

state. Data from the scan path is shifted into the linear

feedback shift register and compacted. This allows a serial

stream of data to be compressed into a 16-bit signature

that can subsequently be shifted out using the LFSRSEL

instruction. The linear feedback shift register is not placed

in the scan chain during this mode. Instead, the register

samples the active scan-chain data as it flows from the

LSPN to TDO

LFSROFF: This instruction terminates linear feedback shift

receiving this instruction.

CNTRSEL: This instruction inserts the 32-bit TCK counter

shift register into the active scan chain. This allows the

user to program the number of “n” TCK cycles to send to

the parked local ports once the CNTRON instruction is

issued (e.g., for BIST operations). Note that to ensure com-

pletion of count-down, the SCANPSC110F should receive

at least “n” TCK

pulses.

CNTRON: This instruction enables the TCK counter. The

counter begins counting down on the first rising edge of

TCK

following the Update-IRTAP controller state and is

decremented on each rising edge of TCK

thereafter.

When the TCK counter reaches terminal count, “00000000”

Hex, TCK

of all parked LSP's is held LOW. The

CNTROFF instruction must be issued before unpark-

ing the LSPs of a SCANPSC110F whose counter has

reached terminal count. This function over-rides the

mode register TCK control bit (bit-3).

CNTROFF: This instruction disables the TCK counter, and

TCK

control is returned to the mode register (bit-3).

FIGURE 9. Local Scan Port Synchronization from Parked-TLR Instruction

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SCANPSC110FSC

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