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SCANPSC110F
Tester/SCANPSC110FBridge Interface (Continued)
Register Set
The SCANPSC110F Bridge includes a number of registers
which are used for SCANPSC110F selection and configu-
ration, scan data manipulation, and scan-support opera-
tions. These registers can be grouped as shown in Table 3.
The specific fields and functions of each of these registers
are detailed in the section of this document titled “Data
Register Descriptions”.
Note that when any of these registers is selected for inser-
tion into the SCANPSC110F's scan-chain, scan data
enters through that register's most-significant bit. Similarly,
data that is shifted out of the register is fed to the scan
input of the next-downstream device in the scan-chain.
TABLE 3. Registers
Addressing Scheme
The SCANPSC110F Bridge architecture extends the func-
tionality of the IEEE 1149.1 Standard by supplementing
that protocol with an addressing scheme which allows a
test controller to communicate with specific
SCANPSC110Fs within a network of SCANPSC110Fs.
That network can include both multi-drop and hierarchical
connectivity. In effect, the SCANPSC110F architecture
allows a test controller to dynamically select specific por-
tions of such a network for participation in scan operations.
This allows a complex system to be partitioned into smaller
blocks for testing purposes.
The SCANPSC110F provides two levels of test-network
partitioning capability. First, a test controller can select
entire individual SCANPSC110Fs, specific sets of
SCANPSC110Fs (multi-cast groups), or all
SCANPSC110Fs (broadcast). This SCANPSC110F-selec-
tion process is supported by a “Level-1” communication
protocol. Second, within each selected SCANPSC110F, a
test controller can select one or more of the chip's three
local scan-ports. That is, individual local ports can be
selected for inclusion in the (single) scan-chain which a
SCANPSC110F presents to the test controller. This mecha-
nism allows a controller to select specific terminal scan-
chains within the overall scan network. The port-selection
process is supported by a “Level-2” protocol.
Hierarchical Test Support
Multiple SCANPSC110F Bridges can be used to assemble
a hierarchical boundary-scan tree. In such a configuration,
the system tester can configure the local ports of a set of
SCANPSC110Fs so as to connect a specific set of local
scan-chains to the active scan chain. Using this capability,
the tester can selectively communicate with specific por-
tions of a target system.
The tester's scan port is connected to the backplane scan
port of a “root” layer of SCANPSC110Fs, each of which can
be selected using multi-drop addressing. A second tier of
SCANPSC110Fs can be connected to this root layer, by
connecting a local port (LSP) of a root-layer
SCANPSC110F to the backplane port of a second-tier
SCANPSC110F. This process can be continued to con-
struct a multi-level scan hierarchy.
SCANPSC110F local ports which are not cascaded into
higher-level SCANPSC110Fs can be thought of as the ter-
minal “leaves” of a scan “tree”. The test master can select
one or more target leaves by selecting and configuring the
local ports of an appropriate set of SCANPSC110Fs in the
test tree.
Register Name BSDL Name Description
Instruction Register INSTRUCTION SCANPSC110F addressing and instruction-decode
IEEE Std. 1149.1 required register
Boundary-Scan Register BOUNDARY IEEE Std. 1149.1 required register
Bypass Register BYPASS IEEE Std. 1149.1 required register
Device Identification Register IDCODE IEEE Std. 1149.1 optional register
Multi-Cast Group Register MCGR SCANPSC110F-group address assignment
Mode Register MODE SCANPSC110F local-port configuration and control bits
Linear-Feedback Shift Register LFSR SCANPSC110F scan-data compaction (signature generation)
TCK Counter Register CNTR Local-port TCK clock-gating (for BIST)
