NXP Semiconductors
MC33771B_SDS
Battery cell controller IC
MC33771BSDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Short data sheet: technical data Rev. 5.0 — 2 May 2018
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Symbol Parameter Min Typ Max Unit
t
RESETFLT
RESET de-glitch filter — 100 — µs
R
RESET_PD
Input logic pull down (RESET) — 100 — kΩ
SPI_COM_EN input
V
IH
Input high-voltage (3.3 V compatible) 2.0 — — V
V
IL
Input low-voltage (3.3 V compatible) — — 1.0 V
V
HYS
Input hysteresis — 450 — mV
R
SPI_COM_EN_PD
Input pull-down resistor (SPI_COM_EN) — 100 — kΩ
Bus switch for TPL communication
RX
TERM
Bus termination resistor (open resistor when bus switch is closed) — 150 — Ω
Remark: If the bus switch is closed, then the termination resistor is open, else the termination resistor is connected. At the end of the daisy
chain, the switch must be open, so that the transmission line is properly terminated.
Digital interface
V
FAULT_HA
FAULT output (high active, IOH = 1.0 mA) 4.0 4.9 6.0 V
I
FAULT_CL
FAULT output current limit 3.0 — 40 mA
R
FAULT_PD
FAULT output pull-down resistance — 100 — kΩ
V
IH_COMM
Voltage threshold to detect the input as high
SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL (NOTE: needs
to be 3.3 V compatible)
—
—
2.0
V
V
IL_COMM
Voltage threshold to detect the input as low
SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL
0.8
—
—
V
V
HYS
Input hysteresis
SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL
—
80
—
mV
I
LOGIC_SS
Sleep state input logic current
CSB
−100
—
100
nA
R
SCLK_PD
Input logic pull-down resistance (SCLK/RDTX_IN–, SI/RDTX+) — 20 — kΩ
R
I_PU
Input logic pull-up resistance to V
COM
(CSB, SDA, SCL) — 100 — kΩ
I
SO_TRI
Tristate SO input current 0 V to V
COM
−2.0 — 2.0 µA
V
SO_HIGH
SO high-state output voltage with I
SO(HIGH)
= −2.0 mA V
COM
−
0.4
— — V
V
SO_LOW
SO, SDA, SLK low-state output voltage with I
SO(HIGH)
= −2.0 mA — — 0.4 V
CSB
WU_FLT
CSB wake-up de-glitch filter, low to high transition — 50 — µs
System timing
t
CELL_CONV
Time needed to acquire all 14 cell voltages and the current after an
on demand conversion
13-bit resolution
14-bit resolution
15-bit resolution
16-bit resolution
—
—
—
—
59
80
123
208
—
—
—
—
µs
t
SYNC
V/I synchronization time
ADC1-A,B at 13 bit, ADC2 at 13 bit
ADC1-A,B at 14 bit, ADC2 at 13 bit
ADC1-A,B at 15 bit, ADC2 at 13 bit
ADC1-A,B at 16 bit, ADC2 at 13 bit
—
—
—
—
48.16
53.50
64.16
85.50
—
—
—
—
µs
