Philips Semiconductors Product data
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
2
C, PWM,
capture/compare, high I/O
2002 Mar 25
63
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Analog Inputs (Continued)
AV
IN
Analog input voltage AV
SS
–0.2 AV
DD
+0.2 V
AV
REF
Reference voltage:
AV
REF–
AV
SS
–0.2 V
AV
REF+
AV
DD
+0.2 V
R
REF
Resistance between AV
REF+
and AV
REF–
10 50 kΩ
C
IA
Analog input capacitance 15 pF
t
ADS
Sampling time (10 bit mode) 8t
CY
µs
t
ADS8
Sampling time (8 bit mode) 5t
CY
µs
t
ADC
Conversion time (including sampling time, 10 bit mode) 50t
CY
µs
t
ADC8
Conversion time (including sampling time, 8 bit mode) 24t
CY
µs
DL
e
Differential non-linearity
10,
11,
12
±1 LSB
IL
e
Integral non-linearity
10,
13
(10 bit mode) ±2 LSB
IL
e8
Integral non-linearity (8 bit mode) ±1 LSB
OS
e
Offset error
10,
14
(10 bit mode) ±2 LSB
OS
e8
Offset error (8 bit mode) ±1 LSB
G
e
Gain error
10,
15
±0.4 %
A
e
Absolute voltage error
10,
16
±3 LSB
M
CTC
Channel to channel matching ±1 LSB
C
t
Crosstalk between inputs of port 5
17,
18
0–100kHz –60 dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 57 through 61 for I
DD
test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10ns; V
IL
= V
SS
+ 0.5 V;
V
IH
= V
DD
– 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V
DD
; STADC = V
SS
.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10ns; V
IL
= V
SS
+ 0.5 V;
V
IH
= V
DD
– 0.5 V; XTAL2 not connected; Port 0 = EW = V
DD
; EA = RST = STADC = V
SS
.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW
= V
DD
;
EA
= RST = STADC = XTAL1 = V
SS
.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V
IN
is approximately 2 V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9 V
DD
specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: V
DD
– 0.2 V < AV
DD
< V
DD
+ 0.2 V.
10.Conditions: AV
REF–
= 0 V; AV
DD
= 5.0 V. Measurement by continuous conversion of AV
IN
= –20mV to 5.12 V in steps of 0.5mV, derivating
parameters from collected conversion results of ADC. AV
REF+
(87C554) = 4.977 V. ADC is monotonic with no missing codes.
11. The differential non-linearity (DL
e
) is the difference between the actual step width and the ideal step width. (See Figure 48.)
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL
e
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 48.)
14.The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 48.)
15.The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 48.)
16.The absolute voltage error (A
e
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
18.This parameter is guaranteed by design and characterized, but is not production tested.
