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P87C554SFAA,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77
Philips Semiconductors Product data
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
2
C, PWM,
capture/compare, high I/O
2002 Mar 25
68
t
LLAX
ALE
PSEN
PORT 0
PORT 2
WR
A0–A7
FROM RI OR DPL
DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
t
WHLH
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
t
DW
SU00213
Figure 51. External Data Memory Write Cycle
V
CC
–0.5
0.45V
0.7V
CC
0.2V
CC
–0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
SU00009
Figure 52. External Clock Drive XTAL1
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
SET TI
SET RI
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
SU00027
1230 4567
VALID VALID VALID VALID VALID VALID VALID VALID
Figure 53. Shift Register Mode Timing
Philips Semiconductors Product data
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
2
C, PWM,
capture/compare, high I/O
2002 Mar 25
69
2.4V
0.45V
2.0V
0.8V
NOTE:
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’.
Test Points
2.0V
0.8V
SU00215
Figure 54. AC Testing Input/Output
2.4V
NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels.
2.4V
0.45V 0.45V
Float
2.0V
0.8V
2.0V
0.8V
SU00216
Figure 55. AC Testing Input, Float Waveform
t
RD
t
SU;STA
t
BUF
t
SU;STO
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
FD
t
RC
t
FC
t
HIGH
t
LOW
t
HD;STA
t
SU;DAT1
t
HD;DAT
t
SU;DAT2
t
SU;DAT3
START condition
repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
STOP condition
START or repeated START condition
SU00107A
Figure 56. Timing SIO1 (I
2
C) Interface
Philips Semiconductors Product data
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
2
C, PWM,
capture/compare, high I/O
2002 Mar 25
70
16
12
8
4
124168
f (MHz)
I
DD
mA
20
0
0
SU01116
MAXIMUM ACTIVE MODE
TYPICAL ACTIVE MODE
MAXIMUM IDLE MODE
TYPICAL IDLE MODE
Figure 57. 16 MHz Version Supply Current (I
DD
) as a Function of Frequency at XTAL1 (f
OSC
)
V
DD
P0
EA
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
V
DD
I
DD
(NC)
CLOCK SIGNAL
V
DD
P1.6
P1.7
STADC
AV
SS
AV
ref–
EW
SU00218
Figure 58. I
DD
Test Condition, Active Mode
All other pins are disconnected
1
1. Active Mode:
a. The following pins must be forced to V
DD
: EA, RST, Port 0, and EW.
b. The following pins must be forced to V
SS
: STADC, AV
ss
, and AV
ref–
.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins
cannot exceed the I
OL1
spec of these pins.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P77

P87C554SFAA,512

Mfr. #:
Buy P87C554SFAA,512
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 16K/512 OTP
Lifecycle:
New from this manufacturer.
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