Philips Semiconductors Product data
P87C554
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
2
C, PWM,
capture/compare, high I/O
2002 Mar 25
65
AC ELECTRICAL CHARACTERISTICS
16 MHz
CLOCK
VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
49 Oscillator frequency
5
Speed versions : 4; 5;S 3.5 16 MHz
t
LHLL
49 ALE pulse width 85 2t
CLCL
–40 ns
t
AVLL
49 Address valid to ALE low 22 t
CLCL
–40 ns
t
LLAX
49 Address hold after ALE low 32 t
CLCL
–30 ns
t
LLIV
49 ALE low to valid instruction in 150 4t
CLCL
–100 ns
t
LLPL
49 ALE low to PSEN low 32 t
CLCL
–30 ns
t
PLPH
49 PSEN pulse width 142 3t
CLCL
–45 ns
t
PLIV
49 PSEN low to valid instruction in 82 3t
CLCL
–105 ns
t
PXIX
49 Input instruction hold after PSEN 0 0 ns
t
PXIZ
49 Input instruction float after PSEN 37 t
CLCL
–25 ns
t
AVIV
5
49 Address to valid instruction in 207 5t
CLCL
–105 ns
t
PLAZ
49 PSEN low to address float 10 10 ns
Data Memory
t
RLRH
50, 51 RD pulse width 275 6t
CLCL
–100 ns
t
WLWH
50, 51 WR pulse width 275 6t
CLCL
–100 ns
t
RLDV
50, 51 RD low to valid data in 147 5t
CLCL
–165 ns
t
RHDX
50, 51 Data hold after RD 0 0 ns
t
RHDZ
50, 51 Data float after RD 65 2t
CLCL
–60 ns
t
LLDV
50, 51 ALE low to valid data in 350 8t
CLCL
–150 ns
t
AVDV
50, 51 Address to valid data in 397 9t
CLCL
–165 ns
t
LLWL
50, 51 ALE low to RD or WR low 137 239 3t
CLCL
–50 3t
CLCL
+50 ns
t
AVWL
50, 51 Address valid to WR low or RD low 122 4t
CLCL
–130 ns
t
QVWX
50, 51 Data valid to WR transition 13 t
CLCL
–50 ns
t
WHQX
50, 51 Data hold after WR 13 t
CLCL
–50 ns
t
QVWH
51 Data valid to WR high 287 7t
CLCL
–150 ns
t
RLAZ
50, 51 RD low to address float 0 0 ns
t
WHLH
50, 51 RD or WR high to ALE high 23 103 t
CLCL
–40 t
CLCL
+40 ns
External Clock
t
CHCX
52 High time 20 20 t
CLCL
–t
CLCX
ns
t
CLCX
52 Low time 20 20 t
CLCL
–t
CHCX
ns
t
CLCH
52 Rise time 20 20 ns
t
CHCL
52 Fall time 20 20 ns
Shift Register
t
XLXL
53 Serial port clock cycle time 750 12t
CLCL
ns
t
QVXH
53 Output data setup to clock rising edge 492 10t
CLCL
–133 ns
t
XHQX
53 Output data hold after clock rising edge 8 2t
CLCL
–117 ns
t
XHDX
53 Input data hold after clock rising edge 0 0 ns
t
XHDV
53 Clock rising edge to input data valid 492 10t
CLCL
–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.
