© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1 Publication Order Number:
NTD4302/D
NTD4302
Power MOSFET
68 A, 30 V, N−Channel DPAK/IPAK
Features
• Ultra Low R
DS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• I
DSS
Specified at Elevated Temperature
• DPAK Mounting Information Provided
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery Powered Products:
i.e., Computers, Printers, Cellular and Cordless Telephones,
and PCMCIA Cards
MAXIMUM RATINGS (T
C
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage V
DSS
30 Vdc
Gate−to−Source Voltage − Continuous V
GS
±20 Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T
C
= 25°C
Continuous Drain Current @ T
C
= 25°C (Note 4)
Continuous Drain Current @ T
C
= 100°C
R
q
JC
P
D
I
D
I
D
1.65
75
68
43
°C/W
W
A
A
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 100°C
Pulsed Drain Current (Note 3)
R
q
JA
P
D
I
D
I
D
I
DM
67
1.87
11.3
7.1
36
°C/W
W
A
A
A
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 100°C
Pulsed Drain Current (Note 3)
R
q
JA
P
D
I
D
I
D
I
DM
120
1.04
8.4
5.3
28
°C/W
W
A
A
A
Operating and Storage Temperature Range T
J
, T
stg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 30 Vdc, V
GS
= 10 Vdc,
Peak I
L
= 17 Apk, L = 5.0 mH, R
G
= 25 W)
E
AS
722 mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
4. Current Limited by Internal Lead Wires.
http://onsemi.com
MARKING DIAGRAMS
& PIN ASSIGNMENTS
A = Assembly Location*
Y = Year
WW = Work Week
T4302 = Device Code
G = Pb−Free Package
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
(Surface Mount)
STYLE 2
AYWW
T
4302G
1
2
3
4
1
Gate
3
Source
2
Drain
4
Drain
IPAK
CASE 369D
(Straight Lead)
STYLE 2
1
2
3
4
N−Channel
D
S
G
30 V
7.8 mW @ 10 V
R
DS(on)
TYP
68 A
I
D
MAXV
(BR)DSS
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
AYWW
T
4302G
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
