IDT74SSTU32865BKG8

10
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOH VDD = 1.7V to 1.9V, IOH = – 6 mA 1.2 V
VOL VDD = 1.7V to 1.9V, IOL = 6 mA 0.5 V
II All Inputs VI = VDD or GND ±5 μA
I
DD Static Standby IO = 0, VDD = 1.9V, RESET = GND 200 μA
Static Operating IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——40mA
I
DDD Dynamic Operating IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),—μA/Clock
(Clock Only) CLK and CLK Switching 50% Duty Cycle. MHz
IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode
Dynamic Operating V
I = VIH (AC) or VIL (AC), CLK and CLK Switching at μA/Clock
(Per Each Data Input) 50% Duty Cycle. One Data Input Switching at 1:2 Mode MHz/Data
Half Clock Frequency, 50% Duty Cycle. Input
Dn V
I = VREF ± 250mV, VDD = 1.8V 2.5 3.5
C
I DCSn and CSGateENable 4 6 pF
CLK and CLK VICR = 0.9V, VID = 600mV, VDD = 1.8V 4 6
RESET V
I = VDD or GND, VDD = 1.8V 2 6
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V
OPERATING CHARACTERISTICS, TA = 25ºC
(1,2)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 1.7 1.9 V
VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V
VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V
VI Input Voltage 0 VDD V
VIH AC High-Level Input Voltage Data Inputs VREF+ 250mV V
VIL AC Low-Level Input Voltage Data Inputs VREF– 250mV V
VIH DC High-Level Input Voltage Data Inputs VREF+ 125mV V
VIL DC Low-Level Input Voltage Data Inputs VREF– 125mV V
VIH High-Level Input Voltage RESET, Cx 0.65 * VDD ——V
VIL Low-Level Input Voltage RESET, Cx 0.35 * VDD V
VICR Common Mode Input Voltage CLK, CLK 0.675 1.125 V
VID Differential Input Voltage CLK, CLK 600 mV
IOH High-Level Output Current 8 mA
IOL Low-Level Output Current 8 mA
T
A Operating Free-Air Temperature 0 70 ° C
NOTES:
1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
2. The differential inputs must not be floating unless RESET is LOW.
11
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
(1)
VDD = 1.8V ± 0.1V
Symbol Parameter Min Max. Unit
fMAX 270 MH z
tPDM
(2)
CLK and CLK to Q 1.41 2.15 ns
tLH LOW to HIGH Delay, CLK and CLK to PYTERR 1.2 3 ns
tHL HIGH to LOW Delay, CLK and CLK to PYTERR 13ns
tPLH LOW to HIGH Propagation Delay, RESET to PYTERR —3ns
tPDMSS
(2,3)
CLK and CLK to Q (simultaneous switching) 2.35 ns
tRPHL RESET to Q 3 ns
dV/dt_r Output slew rate from 20% to 80% 1 4 V/ns
dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns
dV/dt_Δ
(4)
Output slew rate from 20% to 80% 1 V/ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. This parameter is not production tested.
4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
12
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
CL = 30 pF
RL = 1KΩ
DUT
Out
RL = 100Ω
CLK Inputs
T
L = 50Ω
T
L = 350ps, 50Ω
Test Point
V
DD
0V
V
DD/2
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
CLK
V
ICR
VID
tPLH tPHL
Output
V
OH
VOL
VICR
VTT VTT
VOH
VOL
VIH
VIL
tRPHL
VDD/2
V
TT
LVCMOS
RESET
Input
Output
VICR
VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR VID
tSU tH
CLK
CLK
VDD
RL = 1KΩ
Test Point
Test Point
CLK
CLK
CLK
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA
3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times

IDT74SSTU32865BKG8

Mfr. #:
Manufacturer:
Description:
IC BUFFER 28BIT 1:2 REG 160TFBGA
Lifecycle:
New from this manufacturer.
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