IDT74SSTU32865BKG8

7
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
REGISTER TIMING
CLK
CLK
Dn
PARIN
Qn
PTYERR
tPDM,
tPDMSS
n - 1 n n +1 n + 2 n + 3 n + 4 n + 5
t
SU tH
tSU tH
tPDM tPDH
PYTERR
PARIN
Dn
D
Q
D
D
D
CLOCK
LATCHING AND
RESET FUNCTION
(1)
QnA
QnB
22 22
PARITY LOGIC DIAGRAM
NOTE:
1. This function holds the error for two cycles. See REGISTER TIMING diagram.
8
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max. Unit
VDD Supply Voltage Range –0.5 to 2.5 V
VI
(2,3)
Input Voltage Range –0.5 to 2.5 V
VO
(2,3)
Output Voltage Range –0.5 to VDD +0.5 V
I
IK Input Clamp Current VI < 0 ±50 mA
VI > VDD
IOK Output Clamp Current VO < 0 ±50 mA
VO > VDD
IO Continuous Output Current, ±50 mA
VO = 0 to VDD
VDD Continuous Current through each ±100 mA
VDD or GND
T
STG Storage Temperature Range –65 to +150 ° C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. This value is limited to 2.5V maximum.
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
VDD = 1.8V ± 0.1V
Symbol Parameter Min. Max. Unit
fCLOCK Clock Frequency 270 MHz
tw Pulse Duration, CLK, CLK HIGH or LOW 1 ns
tACT
(1,2)
Differential Inputs Active Time 10 ns
tINACT
(1,3)
Differential Inputs Inactive Time 15 ns
t
SU Setup Time DCSn before CLK, CLK 0.7 ns
Data, PARIN, DODT, and DCKE before CLK, CLK 0.5
tH Hold Time Data, DCSn, PARIN, DCKE, and DODT 0.5 ns
after CLK, CLK
NOTES:
1. This parameter is not production tested.
2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH.
3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.
9
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
TERMINAL FUNCTIONS
Signal Terminal
Group Name Type Description
Ungated Inputs DCKE0, DCKE1 SSTL_18 DRAM function pins not associated with Chip Select
DODT0, DODT1
Chip Select D0:D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW
Gated Inputs
Chip Select Inputs DCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at
least one will be LOW when a valid address/command is present. The register can be programmed
to re-drive all D-inputs only (CSGateEN HIGH) when at least one Chip Select input is LOW.
Re-Driven Outputs Q0A:Q21A SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge
Q0B:Q21B of the clock
QCS0-1A, B
QCKE0-1A, B
QODT0-1A, B
Parity Input PARIN SSTL_18 Input parity is received on pin PARIN, and should maintain odd parity across the D0:D21 inputs, at the
rising edge of the clock
Parity Error Output PTYERR Open Drain When LOW, this output indicates that a parity error was identified associated with the address and/or
command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in
JEDEC definition).
Program Inputs CSGateEN 1.8V LVCMOS Chip Select Gate Enable. When HIGH, the D0:D21 inputs will be latched only when at least one Chip
Select input is LOW during the rising edge of the clock. When LOW, the D0:D21 inputs will be latched
and redriven on every rising edge of the clock.
Clock Inputs CLK, CLK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on
the positive clock input (CLK).
Miscellaneous MCL, MCH Must be connected to a Logic LOW or HIGH.
Inputs RESET 1.8V LVCMOS Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR signal.
V
REF 0.9V nominal Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased
reliability.

IDT74SSTU32865BKG8

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Manufacturer:
Description:
IC BUFFER 28BIT 1:2 REG 160TFBGA
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New from this manufacturer.
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