AD7854LARZ Datasheet AD7854ARZ, AD7854ARSZ, AD7854LARSZ | P1-P3

FUNCTIONAL BLOCK DIAGRAM

CALIBRATION

MEMORY

AND CONTROLLER

2.5V

REFERENCE

AGND

CLKIN

CONVST

BUSY

REF2

REF1

REF

OUT

AIN(–)

AIN(+)

DGND

DB11–DB0

HBEN

PARALLEL INTERFACE/CONTROL REGISTER

AD7854/AD7854L

CHARGE

REDISTRIBUTION

DAC

T/H

COMP

SAR + ADC

CONTROL

BUF

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

3 V to 5 V Single Supply, 200 kSPS

12-Bit Sampling ADCs

AD7854/AD7854L

FEATURES

Specified for V

of 3 V to 5.5 V

Read-Only Operation

AD7854–200 kSPS; AD7854L–100 kSPS

System and Self-Calibration

Low Power

Normal Operation

AD7854: 15 mW (V

= 3 V)

AD7854L: 5.5 mW (V

= 3 V)

Automatic Power-Down After Conversion (25 ␮W)

AD7854: 1.3 mW 10 kSPS

AD7854L: 650 ␮W 10 kSPS

Flexible Parallel Interface

12-Bit Parallel/8-Bit Parallel (AD7854)

28-Lead DIP, SOIC and SSOP Packages (AD7854)

APPLICATIONS

Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)

Pen Computers

Instrumentation and Control Systems

High Speed Modems

PRODUCT HIGHLIGHTS

1. Operation with either 3 V or 5 V power supplies.

2. Flexible power management options including automatic

power-down after conversion. By using the power manage-

ment options a superior power performance at slower

throughput rates can be achieved:

AD7854: 1 mW typ @ 10 kSPS

AD7854L: 1 mW typ @ 20 kSPS

3. Operates with reference voltages from 1.2 V to AV

4. Analog input ranges from 0 V to AV

5. Self-calibration and system calibration.

6. Versatile parallel I/O port.

7. Lower power version AD7854L.

GENERAL DESCRIPTION

The AD7854/AD7854L is a high speed, low power, 12-bit ADC

that operates from a single 3 V or 5 V power supply, the

AD7854 being optimized for speed and the AD7854L for low

power. The ADC powers up with a set of default conditions at

which time it can be operated as a read-only ADC. The ADC

contains self-calibration and system calibration options to en-

sure accurate operation over time and temperature and has a

number of power-down options for low power applications.

The AD7854 is capable of 200 kHz throughput rate while the

AD7854L is capable of 100 kHz throughput rate. The input

track-and-hold acquires a signal in 500 ns and features a pseudo-

differential sampling scheme. The AD7854 and AD7854L input

voltage range is 0 to V

REF

(unipolar) and –V

REF

/2 to +V

REF

/2,

centered at V

REF

/2 (bipolar). The coding is straight binary in

unipolar mode and twos complement in bipolar mode. Input

signal range is to the supply and the part is capable of convert-

ing full-power signals to 100 kHz.

CMOS construction ensures low power dissipation of typically

5.4 mW for normal operation and 3.6 µW in power-down mode.

The part is available in 28-lead, 0.6 inch wide dual-in-line pack-

age (DIP), 28-lead small outline (SOIC) and 28-lead small

shrink outline (SSOP) packages.

See Page 27 for data sheet index.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2000

Parameter A Version

B Version

S Version

Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio

70 71 70 dB min Typically SNR is 72 dB

(SNR) V

= 10 kHz Sine Wave, f

SAMPLE

= 200 kHz

(L Version: f

SAMPLE

= 100 kHz @ f

CLKIN

= 2 MHz)

Total Harmonic Distortion (THD) –78 –78 –78 dB max V

= 10 kHz Sine Wave, f

SAMPLE

= 200 kHz

(L Version: f

SAMPLE

= 100 kHz @ f

CLKIN

= 2 MHz)

Peak Harmonic or Spurious Noise –78 –78 –78 dB max V

= 10 kHz Sine Wave, f

SAMPLE

= 200 kHz

(L Version: f

SAMPLE

= 100 kHz @ f

CLKIN

= 2 MHz)

Intermodulation Distortion (IMD)

Second Order Terms –78 –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

SAMPLE

= 200 kHz

(L Version: f

SAMPLE

= 100 kHz @ f

CLKIN

= 2 MHz)

Third Order Terms –78 –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f

SAMPLE

= 200 kHz

(L Version: f

SAMPLE

= 100 kHz @ f

CLKIN

= 2 MHz)

DC ACCURACY

Resolution 12 12 12 Bits

Integral Nonlinearity ±1 ±0.5 ±1 LSB max 5 V Reference V

= 5 V

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits

Unipolar Offset Error ±3 ±3 ±4 LSB max

±2 ±2 ±2 LSB typ

Unipolar Gain Error ±4 ±4 ±4 LSB max

±2 ±2 ±2 LSB typ

Bipolar Positive Full-Scale Error ± 4 ± 4 ± 5 LSB max

±2 ±2 ±2 LSB typ

Negative Full-Scale Error ±4 ±4 ±5 LSB max

±2 ±2 ±2 LSB typ

Bipolar Zero Error ±4 ±4 ±5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to V

REF

0 to V

REF

Volts i.e., AIN(+) – AIN(–) = 0 to V

REF

, AIN(–) can be

biased up but AIN(+) cannot go below AIN(–).

±V

REF

/2 ±V

REF

/2 ±V

REF

/2 Volts i.e., AIN(+) – AIN(–) = –V

REF

/2 to +V

REF

/2, AIN(–)

should be biased to +V

REF

/2 and AIN(+) can go below

AIN(–) but cannot go below 0 V.

Leakage Current ±1 ±1 ±1 µA max

Input Capacitance 20 20 20 pF typ

REFERENCE INPUT/OUTPUT

REF

Input Voltage Range 2.3/V

2.3/V

V min/max Functional from 1.2 V

Input Impedance 150 150 150 kΩ typ

REF

OUT

Output Voltage 2.3/2.75 2.3/2.7 2.3/2.7 V min/max

REF

OUT

Tempco 20 20 20 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V

INH

3 3 3 V min AV

= DV

= 4.5 V to 5.5 V

2.1 2.1 2.1 V min AV

= DV

= 3.0 V to 3.6 V

Input Low Voltage, V

INL

0.4 0.4 0.4 V max AV

= DV

= 4.5 V to 5.5 V

0.6 0.6 0.6 V max AV

= DV

= 3.0 V to 3.6 V

Input Current, I

±10 ± 10 ±10 µA max Typically 10 nA, V

= 0 V or V

Input Capacitance, C

10 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V

SOURCE

= 200 µA

4 4 4 V min AV

= DV

= 4.5 V to 5.5 V

2.4 2.4 2.4 V min AV

= DV

= 3.0 V to 3.6 V

Output Low Voltage, V

0.4 0.4 0.4 V max I

SINK

= 0.8 mA

Floating-State Leakage Current ±10 ±10 ±10 µA max

Floating-State Output Capacitance

10 10 10 pF max

Output Coding Straight (Natural) Binary Unipolar Input Range

Twos Complement Bipolar Input Range

CONVERSION RATE t

CLKIN

× 18

Conversion Time 4.6 (10) 4.6 (9) 4.6 (9) µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)

Track/Hold Acquisition Time 0.5 (1) 0.5 (1) 0.5 (1) µs min (L Versions Only, –40°C to +85°C, 1 MHz CLKIN)

AD7854/AD7854L–SPECIFICATIONS

1, 2

(AV

= DV

= +3.0 V to +5.5 V, REF

/REF

OUT

= 2.5 V

External Reference, f

CLKIN

= 4 MHz (for L Version: 1.8 MHz (0ⴗC to +70ⴗC) and 1 MHz (–40ⴗC to +85ⴗC)); f

SAMPLE

= 200 kHz (AD7854), 100 kHz

(AD7854L); T

= T

MIN

to T

MAX

, unless otherwise noted.) Specifications in () apply to the AD7854L.

–2–

REV. B

Parameter A Version

B Version

S Version

Units Test Conditions/Comments

POWER REQUIREMENTS

DD,

+3.0/+5.5 +3.0/+5.5 +3.0/+5.5 V min/max

Normal Mode

5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV

= DV

= 4.5 V to 5.5 V. Typically 4.5 mA

(1.5 mA);

5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV

= DV

= 3.0 V to 3.6 V. Typically 4.0 mA

(1.5 mA).

Sleep Mode

With External Clock On 10 10 10 µA typ Full power-down. Power management bits in control

400 400 400 µA typ Partial power-down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

With External Clock Off 5 5 5 µA max Typically 1 µA. Full power-down. Power management

bits in control register set as PMGT1 = 1,

PMGT0 = 0.

200 200 200 µA typ Partial power-down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Normal Mode Power Dissipation 30 (10) 30 (10) 30 (10) mW max V

= 5.5 V: Typically 25 mW (8)

20 (6.5) 20 (6.5) 20 (6.5) mW max V

= 3.6 V: Typically 15 mW (5.4)

Sleep Mode Power Dissipation

With External Clock On 55 55 55 µW typ V

= 5.5 V

36 36 36 µW typ V

= 3.6 V

With External Clock Off 27.5 27.5 27.5 µW max V

= 5.5 V: Typically 5.5 µW

18 18 18 µW max V

= 3.6 V: Typically 3.6 µW

SYSTEM CALIBRATION

Offset Calibration Span

+0.05 × V

REF

/–0.05 × V

REF

V max/min Allowable Offset Voltage Span for Calibration

Gain Calibration Span

+0.025 × V

REF

/–0.025 × V

REF

V max/min Allowable Full-Scale Voltage Span for Calibration

NOTES

Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.

Specifications apply after calibration.

Not production tested. Guaranteed by characterization at initial product release.

Sample tested @ +25°C to ensure compliance.

All digital inputs @ DGND except for CONVST @ DV

. No load on the digital outputs. Analog inputs @ AGND.

CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DV

. No load on the digital outputs. Analog inputs @ AGND.

The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans

and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V

REF

and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V

REF

± 0.025 × V

REF

(unipolar mode) and V

REF

/2 ± 0.025 × V

REF

(bipolar mode)). This is explained in more detail in the calibration section of the data sheet.

Specifications subject to change without notice.

REV. B

–3–

AD7854/AD7854L

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD7854LARZ

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Buy AD7854LARZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B Parallel

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AD7854LARZ

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