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AD7854LARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD7854/AD7854L
–4–
REV. B
Limit at T
MIN
, T
MAX
(A, B, S Versions)
Parameter 5 V 3 V Units Description
f
CLKIN
2
500 500 kHz min Master Clock Frequency
4 4 MHz max
1.8 1.8 MHz max L Version
t
1
3
100 100 ns min CONVST Pulsewidth
t
2
50 90 ns max CONVST to BUSY ↑ Propagation Delay
t
CONVERT
4.5 4.5 µs max Conversion Time = 18 t
CLKIN
10 10 µs max L Version 1.8 MHz CLKIN. Conversion Time = 18 t
CLKIN
t
3
15 15 ns min HBEN to RD Setup Time
t
4
5 5 ns min HBEN to RD Hold Time
t
5
0 0 ns min CS to RD to Setup Time
t
6
0 0 ns min CS to RD Hold Time
t
7
55 70 ns min RD Pulsewidth
t
8
4
50 50 ns max Data Access Time After RD
t
9
5
5 5 ns min Bus Relinquish Time After RD
40 40 ns max
t
10
60 70 ns min Minimum Time Between Reads
t
11
0 0 ns min HBEN to WR Setup Time
t
12
5 5 ns max HBEN to WR Hold Time
t
13
0 0 ns min CS to WR Setup Time
t
14
0 0 ns max CS to WR Hold Time
t
15
55 70 ns min WR Pulsewidth
t
16
10 10 ns min Data Setup Time Before WR
t
17
5 5 ns min Data Hold Time After WR
t
18
4
1/2 t
CLKIN
1/2 t
CLKIN
ns min New Data Valid Before Falling Edge of BUSY
t
19
50 70 ns min HBEN High Pulse Duration
t
20
50 70 ns min HBEN Low Pulse Duration
t
21
40 60 ns min Propagation Delay from HBEN Rising Edge to Data Valid
t
22
40 60 ns min Propagation Delay from HBEN Falling Edge to Data Valid
t
23
2.5 t
CLKIN
2.5 t
CLKIN
ns max CS↑ to BUSY ↑ in Calibration Sequence
t
CAL
6
31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013
t
CLKIN
)
t
CAL1
6
27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 t
CLKIN
)
t
CAL2
6
3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent
(13889 t
CLKIN
)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down
section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
9
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7854 and 1.8 MHz for AD7854L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
AD7854/AD7854L
REV. B
–5–
ORDERING GUIDE
Linearity Power
Temperature Error Dissipation Package
Model Range
1
(LSB) (mW) Option
2
AD7854AQ –40°C to +85°C 1 15 Q-28
AD7854SQ –55°C to +125°C 1 15 Q-28
AD7854AR –40°C to +85°C 1 15 R-28
AD7854BR –40°C to +85°C 1/2 15 R-28
AD7854ARS –40°C to +85°C 1 15 RS-28
AD7854LAQ
3
–40°C to +85°C 1 5.5 Q-28
AD7854LAR
3
–40°C to +85°C 1 5.5 R-28
AD7854LARS
3
–40°C to +85°C 1 5.5 RS-28
EVAL-AD7854CB
4
EVAL-CONTROL BOARD
5
NOTES
1
Linearity error refers to the integral linearity error.
2
Q = Cerdip; R = SOIC; RS = SSOP.
3
L signifies the low power version.
4
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for
evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards
ending in the CB designator. For more information on Analog Devices products and evaluation boards visit our
World Wide Web home page at http://www.analog.com.
TO
OUTPUT
PIN
+2.1V
I
OH
1.6mA
200µA
I
OL
C
L
50pF
Figure 1. Load Circuit for Digital Output Timing
Specifications
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
REF
IN
/REF
OUT
to AGND . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +300°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θ
JC
Thermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latchup.
PIN CONFIGURATION
FOR DIP, SOIC AND SSOP
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
17
16
15
20
19
18
28
27
26
25
24
23
22
21
AD7854
CONVST
DB10
DB11
CLKIN
BUSY
WR
RD
CS
DV
DD
DGND
DB9
REF
IN
/REF
OUT
AV
DD
AGND
C
REF1
C
REF2
AIN(+)
DB6
DB7
DB8
AIN(–)
HBEN
DB0
DB1
DB5
DB2
DB3
DB4
AD7854/AD7854L
–6–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold
mode and starts conversion. When this input is not used, it should be tied to DV
DD
.
2 WR Write Input. Active low logic input. Used in conjunction with CS and HBEN to write to internal registers.
3 RD Read Input. Active low logic input. Used in conjunction with CS and HBEN to read from internal
registers.
4 CS Chip Select Input. Active low logic input. The device is selected when this input is active.
5 REF
IN
/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
REF
OUT
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears
at the pin. This pin can be overdriven by an external reference and can be taken as high as AV
DD
. When
this pin is tied to AV
DD
, then the C
REF1
pin should also be tied to AV
DD
.
6AV
DD
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
7 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
8C
REF1
Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the
internal DAC. The capacitor should be tied between the pin and AGND.
9C
REF2
Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.
10 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time, and cannot go below AIN(–) when the unipolar input range is selected.
11 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time.
12 HBEN High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a read
cycle with HBEN low. When HBEN is high, then the high byte of data that is written to or read from the
part is on DB0 to DB7. When HBEN is low, then the lowest byte of data being written to the part is on
DB0 to DB7. If reading from the part with HBEN low, then the lowest 12 bits of data appear on pins DB0
to DB11. This allows a single read from the ADC or from the control register in a 16-bit bus system.
However, two reads are needed to access the calibration registers. Also, two writes are necessary to write to
any of the registers.
13–21 DB0–DB8 Data Bits 0 to 8. Three state data I/O pins that are controlled by CS, RD, WR and HBEN. Data output is
straight binary (unipolar mode) or twos complement (bipolar mode).
22 DV
DD
Digital Supply Voltage, +3.0 V to +5.5 V.
23 DGND Digital Ground. Ground reference point for digital circuitry.
24–26 DB9–DB11 Data Bits 9 to 11. Three state data output pins that are controlled by CS, RD and HBEN. Data output is
straight binary (unipolar mode) or twos complement (bipolar mode). These output pins should be tied to
DV
DD
via 100 kΩ resistors when the AD7854/AD7854L is being interfaced to an 8-bit data bus.
27 CLKIN Master Clock Signal for the device (4 MHz for AD7854, 1.8 MHz for AD7854L). Sets the conversion and
calibration times.
28 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until
conversion is completed. BUSY is also used to indicate when the AD7854/AD7854L has completed its on-
chip calibration sequence.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD7854LARZ

Mfr. #:
Buy AD7854LARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B Parallel
Lifecycle:
New from this manufacturer.
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