AD7854LARZ Datasheet AD7854ARZ, AD7854ARSZ, AD7854LARSZ | P7-P9

AD7854/AD7854L

REV. B

–7–

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7854/AD7854L, it is

defined as:

THD (dB) = 20 log

)

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for ADCs

where the harmonics are buried in the noise floor, it will be a

noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

Testing is performed using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used. In

this case, the second order terms are usually distanced in fre-

quency from the original sine waves while the third order terms

are usually at a frequency close to the input frequencies. As a

result, the second and third order terms are specified separately.

The calculation of the intermodulation distortion is as per the

THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)

when operating in the unipolar mode.

Unipolar Gain Error

This is the deviation of the last code transition (111 . . . 110 to

111 . . . 111) from the ideal, i.e., AIN(–) +V

REF

/2 – 1.5 LSB,

after the unipolar offset error has been adjusted out.

Bipolar Positive Full-Scale Error

This applies to the bipolar modes only and is the deviation of the

last code transition from the ideal AIN(+) voltage. For bipolar

mode, the ideal AIN(+) voltage is (AIN(–) +V

REF

/2 – 1.5 LSB).

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the

first code transition (10 . . . 000 to 10 . . . 001) from the ideal

AIN(+) voltage (AIN(–) – V

REF

/2 + 0.5 LSB).

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of

conversion. Track/Hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig-

nals up to half the sampling frequency (f

/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

AD7854/AD7854L

–8–

REV. B

AD7854/AD7854L ON-CHIP REGISTERS

The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the

AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DV

for operating the AD7854/AD7854L as a

read-only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-

bration, and software conversion start can be selected by writing to the part.

The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra-

tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and

calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first

8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the

8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each

transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to

determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the

address bits, while Figure 2 shows the overall write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register.

0 1 This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.

1 0 This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are writ-

ten to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to

the control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first.

Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-

up setting. There is always four leading zeros when reading from the ADC output data register.

0 1 All successive read operations are from the TEST REGISTER.

1 0 All successive read operations are from the CALIBRATION REGISTERS.

1 1 All successive read operations are from the STATUS REGISTER.

TEST

CALIBRATION

REGISTERS

CONTROL

ADDR1, ADDR0

DECODE

01 10 11

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

OFFSET(1) GAIN(1)

CALSLT1, CALSLT0

DECODE

00 01 10 11

Figure 2. Write Register Hierarchy/Address Decoding

TEST

CALIBRATION

REGISTERS

CONTROL

RDSLT1, RDSLT0

DECODE

01 10 11

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

OFFSET(1) GAIN(1)

CALSLT1, CALSLT0

DECODE

00 01 10 11

ADC OUTPUT

DATA REGISTER

Figure 3. Read Register Hierarchy/Address Decoding

AD7854/AD7854L

REV. B

–9–

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The

control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described

below. The power-up status of all bits is 0.

MSB

ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1

RDSLT0 AMODE CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

Control Register Bit Function Description

Bit Mnemonic Comment

13 ZERO These four bits must be set to 0 when writing to the control register.

12 ZERO

11 ZERO

10 ZERO

9 PMGT1 Power Management Bits. These two bits are used for putting the part into various power-down modes

8 PMGT0 (See Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II.

6 RDSLT0

5 AMODE Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit

position selects range 0 to V

REF

(i.e., AIN(+) – AIN(–) = 0 to V

REF

). In this range AIN(+) cannot go

below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this

bit position selects range –V

REF

/2 to +V

REF

/2 (i.e., AIN(+) – AIN(–) = –V

REF

/2 to +V

REF

/2). AIN(+)

cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +V

REF

/2 to allow

AIN(+) to go as low as AIN(–) –V

REF

/2 V. Data coding is twos complement for this range.

4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration

(see Calibration section).

3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-

0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

00 0 A full internal calibration is initiated. First the internal DAC is calibrated, then the

internal gain error and finally the internal offset error are removed. This is the default setting.

0 0 1 First the internal gain error is removed, then the internal offset error is removed.

0 1 0 The internal offset error only is calibrated out.

0 1 1 The internal gain error only is calibrated out.

10 0 A full system calibration is initiated. First the internal DAC is calibrated, followed by the

system gain error calibration, and finally the system offset error calibration.

1 0 1 First the system gain error is calibrated out followed by the system offset error.

1 1 0 The system offset error only is removed.

1 1 1 The system gain error only is removed.

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AD7854LARZ

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Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B Parallel

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AD7854LARZ

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