LTC4370CMS#PBF Datasheet LTC4370IDE#TRPBF, LTC4370IDE#PBF, LTC4370IMS#PBF | P13-P15

LTC4370

4370f

External CPO Supply

The internal charge pump takes milliseconds to charge

up the CPO capacitor especially during device power-up.

This time can be shortened by connecting an external

supply to the CPO pin. A series resistor is needed to limit

the current into the internal clamp between the CPO and

pins. The CPO supply should also be higher than the

main input supply to meet the gate drive requirements

of the MOSFET. Figure 5 shows such a 3.3V load share

application, where a 12V supply is connected to the CPO

pins through a 1k resistor. The 1k limits the current into

the CPO pin when the V

pin is grounded. For the 8.7V

of gate drive (12V – 3.3V), logic-level MOSFETs would be

an appropriate choice for M1 and M2.

Loop Stability

The servo amplifier loop is compensated by the gate

capacitance of the N-channel power MOSFET. No further

compensation components are normally required. In the

case when a MOSFET with less than 1nF gate capacitance

is chosen, a 1nF compensation capacitor connected across

the gate and source might be required.

The load sharing control loop is compensated by the

capacitor from the COMP pin to ground. This

capacitor

should

be at least 50× the input capacitance C

ISS

of the

MOSFET. A larger capacitor improves stability at the ex-

pense of increased sharing closure delay, while a smaller

capacitor can cause the two supply currents to switch back

and forth before settling. The COMP capacitor can be just

10× C

ISS

when a CPO capacitor is omitted, i.e., when fast

gate turn-on is not used (see Figure 6).

Input and Output Capacitance for Pulsed Loads

For pulsed loads, the load current will be shared every cycle

at frequencies below 100Hz. At higher frequencies, each

cycle’s current may not be shared but the time average of

the currents will be. Bypassing capacitance on the inputs

should be provided to minimize glitches and ripple. This

is important since the controller tries to compensate for

the supply voltage differences to achieve load sharing.

Sufficient load capacitance should also be provided to

enhance the DC component of the load current presented

to the load share circuit. It is also important to design

• R

DS(ON)

below 75mV, as mentioned earlier.

With very low duty cycle or very low frequency loads,

the COMP voltage will rail whenever the load

current falls

below

the sharing threshold of V

EA(OS)

for hundreds of

milliseconds. At the start of the next load cycle there will

be a sharing closure delay as COMP slews to its operating

point around 0.7V or 1.24V. To avoid this delay, maintain

the load current above V

EA(OS)

Figure 5. 3.3V Load Share with External 12V Supply

Powering CPO for Faster Start-Up and Refresh

GATE1

CPO1

CPO2

4370 F05

INA

3.3V

INB

3.3V

12V

TO SENSE

RESISTOR

TO SENSE

RESISTOR

39nF

IN1

GATE2V

IN2

LTC4370

applicaTions inForMaTion

Figure 6. Current Sharing 12V Supplies

SUM85N03-06P D1: RED LED, LN1251C

SUM85N03-06P

GATE1CPO1

CPO2

GND

EN1

EN2

RANGE

4370 F06

INA

12V

INB

12V

OUT

10A

IN1

FETON1

COMP

FETON2

OUT1

OUT2

GATE2

IN2

LTC4370

2.5mΩ

0.039µF

VCC

0.1µF

47.5k

2.7k

LTC4370

4370f

Input Transient Protection

When the capacitances at the input and output are very

small, rapid changes in current can cause transients that

exceed the 24V absolute maximum rating of the V

and

OUT pins. In ORing applications, one surge suppressor

connected from OUT to ground clamps all the inputs. In

the absence of a surge suppressor, an output capacitance

of 10μF is sufficient in most applications to prevent the

transient from exceeding 24V.

12V Design Example

This design example demonstrates the selection of

components in a 12V system with a 10A maximum load

current and ±2% tolerance supplies (Figure 6). That is

followed by the recalculations involved for a similar 5V

system (Figure 1).

First, calculate the R

DS(ON)

of the MOSFET to achieve

the desired forward drop at full load. Assuming a V

FWD

of 50mV:

DS(ON)

≤

FWD

LOAD

50mV

10A

= 5mΩ

The SUM85N03-06P offers a good solution in a DD-Pak

(TO-263) sized package with a 4.5mΩ R

DS(ON)

, 30V

DSS

and 20V V

GS(MAX)

. Since 0.5I

• R

DS(ON)

is 22.5mV,

the servo amplifier will be able to regulate the 25mV mini-

mum forward regulation voltage leading to the maximum

possible sharing range set by V

RANGE

2% of 12V is 240mV. The sharing capture range, ΔV

IN(SH)

needs to be about 2× 240mV (±480mV) to work for most

supply voltage differences. A 47.5k R3 sets V

RANGE

475mV. Equation 1 is used to calculate the maximum

forward regulation voltage:

FR(MAX)

= 10µA • 47.5k + 25mV = 500mV

Equation 3 gives the maximum power dissipation in the

MOSFET to be:

D(MAX)

= 10A • 500mV = 5W

Sufficient PCB area with air flow needs to be provided

around the MOSFET drain to keep its junction temperature

below the 175°C maximum.

A 2.5mΩ sense resistor drops 25mV at full load and

yields an error amplifier offset induced sharing error of

2mV/(10A • 2.5mΩ) or 8% (Equation 4). At full load, the

sense resistor dissipates 10A

• 2.5mΩ or 250mW. Since

a 12V supply is large enough to tolerate a diode drop, fast

gate

turn-on is not needed. Hence, the CPO capacitor is

omitted. The input capacitance, C

ISS

, of the MOSFET is

about 3800pF. Since fast turn-on is not used, the COMP

capacitor C

can be just 10× C

ISS

at 0.039µF.

Red LED, D1, turns on when any one of the MOSFETs is

off, indicating a break in sharing. It requires around 3mA

for good luminous intensity. Accounting for a 2V diode

drop and 0.6V V

, R4 is set to 2.7k.

5V Design Example

For a 5V, 10A system with ±3% tolerance supplies and

fast gate turn-on (Figure 1), the following components

need to be recalculated: R3, C1, C2, C

, and R4. R3 is

set to 30.1k to account for possible supply differences

(2 • 3% • 5V yields ±300mV). C1 and C2 are set to 10×

ISS

at 0.039µF. With fast turn-on, C

is selected closer

to 50× C

ISS

at 0.18µF. With the 5V supply, R4 needs to

be 820Ω to allow 3mA into the LED.

applicaTions inForMaTion

LTC4370

4370f

PCB Layout Considerations

Kelvin connection of the OUT pins to the sense resis-

tors is important for accurate current sharing. Place the

MOSFET as close as possible to the sense resistor. Keep the

traces to the MOSFET wide and short to minimize resistive

losses. The PCB traces associated with the power path

through the MOSFET should have low resistance. Thermal

management techniques such as sufficient drain cop-

per area or heat sinks should be considered for optimal

MOSFET power dissipation. See Figure 7.

It is also important to put C

VCC

, the bypass capacitor, as

close as possible between V

and GND. Place C1 and

C2 near the CPO and V

pins. The COMP pin may need

a guard ring to maintain low board leakage.

Figure 7. Recommended PCB Layout for M1, M2, C

VCC

, R1, R2

applicaTions inForMaTion

4370 FO7

MSOP-16

LOAD

CURRENT FLOW

VIA TO

GROUND

PLANE

DD-PAK

FROM

SUPPLY

VCC

W D

DD-PAK

FROM

SUPPLY

TRACK WIDTH

W: 0.03 PER AMPERE

ON 1oz Cu FOIL

DRAWING IS NOT TO SCALE!

LTC4370

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC4370CMS#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Power Management Specialized - PMIC Two-S Diode-OR C Balancing Cntr

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LTC4370CMS#PBF

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