DATASHEET
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY 1
IDT74SSTUBF32865A 7092/11
Description
This 28-bit 1:2 registered buffer with parity is designed for
1.7V to 1.9V V
DD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load. The IDT74SSTUBF32865A
operates from a differential clock (CLK and CLK
). Data are
registered at the crossing of CLK going high, and CLK
going low.
The device supports low-power standby operation. When
the reset input (RESET
) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (V
REF) inputs are allowed. In
addition, when RESET
is low all registers are reset, and all
outputs except PTYERR
are forced low. The LVCMOS
RESET
input must always be held at a valid logic high or
low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR2 RDIMM application, RESET
is specified to be
completely asynchronous with respect to CLK and CLK
.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET
until the input receivers are fully enabled, the
design of the IDT74SSTUBF32865A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The device monitors both DCS0
and DCS1 inputs and will
gate the Qn outputs from changing states when both DCS0
and DCS1
are high. If either DCS0 and DCS1 input is low,
the Qn outputs will function normally. The RESET
input has
priority over the DCS0
and DCS1 control and will force the
Qn outputs low and the PTYERR
output high. If the
DCS-control functionality is not desired, then the
CSGateEnable input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs.
The IDT74SSTUBF32865A includes a parity checking
function. The IDT74SSTUBF32865A accepts a parity bit
from the memory controller at its input pin PARIN,
compares it with the data received on the D-inputs and
indicates whether a parity error has occurred on its
open-drain PTYERR
pin (active LOW).
Features
• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs
and outputs
• Supports LVCMOS switching levels on CSGateEN and
RESET
inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 160-ball LFBGA package
Applications
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
• Ideal for DDR2 400, 533, 667, and 800
