IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY 10
IDT74SSTUBF32865A 7092/11
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol Parameter
V
DD = 1.8V ± 0.1V
UnitsMin. Max.
fCLOCK Clock Frequency 410 MHz
t
W Pulse Duration; CLK, CLK HIGH or LOW 1 ns
t
ACT Differential Inputs Active Time
1
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of t
ACT(max) after RESET is taken HIGH.
10 ns
t
INACT Differential Inputs Inactive Time
2
2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of t
INACT(max) after RESET is taken LOW.
15 ns
t
SU
Setup
Time
DCS0
before CLK↑ , CLK↓, DCS and CSGateEN
HIGH; DCS1
before CLK↑ , CLK↓, DCS0 and
CSGateEN HIGH
3
3 tSU = 700ps for DCSx exiting Suspention Mode.
0.6
ns
DCSn
, DODT, DCKE, and Dn after CLK↑ , CLK↓ 0.5
PARIN after CLK↑ , CLK
↓ 0.5
t
H
Hold
Time
DCSn
, DODT, DCKE, and Dn after CLK↑ , CLK↓ 0.4
ns
PARIN after CLK↑ , CLK
↓ 0.4
Symbol Parameter
V
DD = 1.8V ± 0.1V
UnitsMin. Max.
fMAX Max Input Clock Frequency 410 MHz
t
PDM
1
1 Design target as per JEDEC specifications.
Propagation Delay, single bit switching, CLK↑ / CLK
↓ to Qn 1.1 1.5 ns
tPDQ
2
2 Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn 0.4 0.8 ns
t
PDMSS
1
Propagation Delay, simultaneous switching, CLK↑ / CLK↓ to Qn 1.6 ns
t
LH LOW to HIGH Propagation Delay, CLK↑ / CLK↓ to PTYERR 1.2 3 ns
tHL HIGH to LOW Propagation Delay, CLK↑ / CLK↓ to PTYERR 1.0 3 ns
t
PHL HIGH to LOW Propagation Delay, RESET↓ to Qn↓ 3ns
t
PLH LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑ 3ns
