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74SSTUBF32865ABKG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY 13
IDT74SSTUBF32865A 7092/11
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
Simulation Load Circuit
Voltage and Current Waveforms Inputs Active and Inactive
Times
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Production-Test Load Circuit
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
NOTES:
1. C
L includes probe and jig capacitance.
2. I
DD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. V
TT = VREF = VDD/2
6. V
IH = VREF + 250mV (AC voltage levels) for differential inputs.
V
IH = VDD for LVCMOS input.
7. V
IL = VREF - 250mV (AC voltage levels) for differential inputs.
V
IL = GND for LVCMOS input.
8. V
ID = 600mV.
9. t
PLH and tPHL are the same as tPDM.
CL =12pF
RL =1K
DUT
Out
RL=100
LK Inputs
T
L =50
T
L = 350ps, 50
Test Point
CLK
CLK
VDD
RL =1K
Test Point
Test Point
VDD
0V
V
DD/2
L
VCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
VICR
VID
VICR
I
nput
tW
VREF
VI
H
VI
L
VREF
I
nput
VICR
VI
D
tSU tH
C
LK
C
LK
ZO =50
Test
Point
RL =50
DUT
Out
C
LK Inputs
CLK
VDD/2
CLK
ZO =50
ZO =50
Test
Point
Test
Point
CLK
V
ICR
VID
tPLH tPHL
O
utput
V
OH
VOL
VICR
VTT VTT
CLK
VOH
VOL
VIH
VIL
tRPHL
VDD/2
V
TT
L
VCMOS
RESET
Input
Output
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY 14
IDT74SSTUBF32865A 7092/11
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
Load Circuit: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Load Circuit: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
Load Circuit: Error Output Measurements
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET
input)
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
CL =10pF
RL =50
DUT
Out
Test Poin
t
VDD
VO
H
80%
20%
VO
L
O
utput
dv_f
dt_f
CL =10pF
RL =50
DUT
Out
Test Poi
n
t
VO
L
20%
80%
VO
H
O
utput
dv_r
dt_r
CL =10pF
RL =1K
DUT
Out
Test Poin
t
VDD
VO
H
VC
C
Output
W
aveform 2
LVCMOS
RESET
Input
tPLH
VCC/2
0.15V
0
V
0V
VC
C
VICR
tHL
Timing
Inputs
VICR
VI(PP
)
Output
W
aveform 1
V
CC/2
VO
L
VOH
Output
W
aveform 2
0.15V
0V
VICR
tHL
Timing
Inputs
VICR
VI(PP
)
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY 15
IDT74SSTUBF32865A 7092/11
Ordering Information
XXX XX
PackageDevice Type
BKG Thin Profile, Fine Pitch, Ball Grid Array - Green
28-Bit 1:2 Registered Buffer with Parity865A
32
Double Density
IDT XX
Family
Shipping
Carrier
X
8 Tape and Reel
SSTUBFXX
Temp. Range
74
0°C to +70°C (Commercial)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

74SSTUBF32865ABKG8

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Manufacturer:
IDT
Description:
Registers DDR2 - 800 REGISTER
Lifecycle:
New from this manufacturer.
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