9DBV0931AKLF Datasheet 9DBV0931AKLF, 9DBV0931AKILF | P10-P12

9-OUTPUT 1.8V HCSL FANOUT BUFFER 10 MARCH 14, 2017

9DBV0931 DATASHEET

Additive Phase Jitter Plot: 125M (12kHz to 20MHz)

MARCH 14, 2017 11 9-OUTPUT 1.8V HCSL FANOUT BUFFER

9DBV0931 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a stop bit

Note: SMBus Address is Latched on SADR pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

O O

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

O O

Byte N + X - 1

N Not acknowledge

PstoP bit

9-OUTPUT 1.8V HCSL FANOUT BUFFER 12 MARCH 14, 2017

9DBV0931 DATASHEET

SMBus Table: Output Enable Register

Byte 0 Name Control Function Type 0 1 Default

Bit 7

DIF OE7 Output Enable RW Low/Low OE# pin control 1

Bit 6

DIF OE6 Output Enable RW Low/Low OE# pin control 1

Bit 5

DIF OE5 Output Enable RW Low/Low OE# pin control 1

Bit 4

DIF OE4 Output Enable RW Low/Low OE# pin control 1

Bit 3

DIF OE3 Output Enable RW Low/Low OE# pin control 1

Bit 2

DIF OE2 Output Enable RW Low/Low OE# pin control 1

Bit 1

DIF OE1 Output Enable RW Low/Low OE# pin control 1

Bit 0

DIF OE0 Output Enable RW Low/Low OE# pin control 1

1. A low on these bits will override the OE# pin and force the differential output Low/Low

SMBus Table: Output Enable and Output Amplitude Control Register

Byte 1 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

DIF OE8 Output Enable RW Low/Low OE# pin control 1

Bit 4

Bit 3

Bit 2

Bit 1

AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1

Bit 0

AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0

1. A low on the DIF OE bit will override the OE# pin and force the differential output Low/Low

SMBus Table: DIF Slew Rate Control Register

Byte 2 Name Control Function Type 0 1 Default

Bit 7

SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 RW Slow setting Fast setting 1

Bit 6

SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 RW Slow setting Fast setting 1

Bit 5

SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 RW Slow setting Fast setting 1

Bit 4

SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Slow setting Fast setting 1

Bit 3

SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW Slow setting Fast setting 1

Bit 2

SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW Slow setting Fast setting 1

Bit 1

SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow setting Fast setting 1

Bit 0

SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow setting Fast setting 1

SMBus Table: DIF Slew Rate Control Register

Byte 3 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SLEWRATESEL DIF8 Adjust Slew Rate of DIF8 RW Slow setting Fast setting 1

Byte 4 is Reserved and reads back 'hFF

Reserved

Controls Output Amplitude

Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9DBV0931AKLF

Mfr. #:

Buy 9DBV0931AKLF

Manufacturer:

IDT

Description:

Clock Buffer 9-output 1.8 V PCIe Gen1-2-3 Fanout Buff

Lifecycle:

New from this manufacturer.

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9DBV0931AKLF

9DBV0931AKLF

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