Part / Order Number Shipping Packaging Package Temperature
9DBV0931AKLF Trays 48-pin VFQFPN 0 to +70° C
9DBV0931AKLFT Tape and Reel 48-pin VFQFPN 0 to +70° C
9DBV0931AKILF Trays 48-pin VFQFPN -40 to +85° C
9DBV0931AKILFT Tape and Reel 48-pin VFQFPN -40 to +85° C
Rev. Initiator Issue Date Description Page #
A RDW 7/28/2014
1. Updated front page text
2. Updated block diagram
3. Updated electrical tables
4. Updated test loads diagrams.
5. Updated Smbus byte 2, 3 and 6 labeling. Functionality did not
change.
6. Move to final.
Various
B RDW 8/27/2014
1. Updated min Vhigh on DIF outputs from 630mV to 660mV, correcting
a typo.
2. Corrected Conditions for Slew Rate in DIF Low-Power HCSL Outputs
3. Lowered maximum PCIe Gen3 additive phase jitter from 0.3ps rms to
0.1ps rms.
8
C RDW 8/28/2014
1. Corrected Supply Voltage in Absolute Maximum Ratings.
2. Lowered additive phase jitter specs.
Various
D RDW 3/25/2016
1. Revised front page text extensively.
2. Added note about Spread Spectrum Compatibility to the features.
3. Change pin name of VDDA1.8 to VDD1.8 and GNDA to GND to clarify
that this part does not have a PLL. This is a document change only.
There is no silicon change.
4. Corrected OE8# to indicate an internal pull down, not a pull up.
5. Added epad nomenclature to DS
6. Updated package drawing to latest version - no package change.
7. Added reference to AN-891.
8. Updated "Current Consumption" table to remove references to
VDDA1.8
9. Added "RMS additive phase jitter: 251fs" to phase noise plot
10. Updated "Clock Input Parameters" table for consistency - no silicon
change.
11. Updated "Output Duty Cycle, Jitter, Skew and PLL Characteristics"
and "Phase Jitter" tables to remove references to bypass mode.
1-5,7-9 14
E RDW 3/14/2017
1. Removed "...bypass mode." reference in note 3 under Output Duty
Cycle table.
2. Corrected spelling errors/typos.
3. Change VDDA to VDDO1.8 in Current Consumption table.
4. Update Additive Phase Jitter conditions for PCIe Gen3.
5. Updated package outline drawings.
8,9,15,16
