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9DBV0931AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MARCH 14, 2017 7 9-OUTPUT 1.8V HCSL FANOUT BUFFER
9DBV0931 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx Supply voltage for core and analog 1.7 1.8 1.9 V
Output Supply Voltage VDDIO Low Voltage Supply LP-HCSL Outputs 0.9975 1.05-1.8 1.9 V
T
COM
Commercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= V
DD
-5 5 µA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= V
DD
; Inputs with internal pull-down resistors
-200 200 µA
Input Frequency F
in
1 200 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_I N
DIF_IN differential clock inputs 1.5 2.7 pF 1,6
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
power-up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency PCIe
f
MODI NPCI e
Allowable frequency for PCIe applications
(Triangular modulation)
30 33 kHz
Input SS Modulation
Frequency non-PCIe
f
MODI N
Allowable frequency for non-PCIe applications
(Triangular modulation)
066kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 µs 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.8 V 4
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.3 V 5
SMBus Output Low Voltage V
OLSMB
at I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
at V
OL
4mA
Nominal Bus Voltage V
DDSMB
Bus voltage 1.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max V
IL
- 0.15V) to (Min V
IH
+ 0.15V) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min V
IH
+ 0.15V) to (Max V
IL
- 0.15V) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 7
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
6
DIF_IN input.
7
The differential input clock must be running for the SMBus to be active.
3
Time from deassertion until outputs are > 200 mV.
4
For V
DDSMB
< 3.3V, V
ILSMB
< = 0.35V
DDSMB.
5
For V
DDSMB
< 3.3V, V
IHSMB
> = 0.65V
DDSMB.
Input Current
Capacitance
Ambient Operating
Temperature
9-OUTPUT 1.8V HCSL FANOUT BUFFER 8 MARCH 14, 2017
9DBV0931 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope averaging on, fast slew rate setting 2.3 3.4 4.3
V/ns
1,2,3
Scope averaging on, slow slew rate setting 1.4 2.2 3.1
V/ns
1,2,3
Slew Rate Matching
Δ
Trf Slew rate matching, scope averaging on 5 20
%
1,2,4
Voltage High V
HIGH
660 774 850 7
Voltage Low V
LOW
-150 0 150 7
Max Voltage Vmax 813 1150 7
Min Voltage Vmin -300 -55 7
Vswing Vswing Scope averaging off 300 1548 mV 1,2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 404 550 mV 1,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 12 140 mV 1,6
2
Measured from differential waveform.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
7
660mV Vhigh is the minimum when VDDIO is > = 1.05V +/-5%. If VDDIO is < 1.05V +/-5%, the minimum Vhigh will be VDDIOmin -
250mV. For example, for VDDIO = 0.9V +/-5%, VHIGHmin will be 860mV - 250mV = 610mV.
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. C
L
= 2pF with R
S
= 33
Ω
for Zo = 50
Ω
(100
Ω
differential
trace impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
Slew Rate Trf
Statistical measurement on single-ended signal
using oscilloscope math function.
(Scope averaging on)
mV
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDR
VDDR at 100MHz 2.5 5 mA 1
I
DDDIG
VDDIG, all outputs at 100MHz 5.7 8 mA 1
I
DDO
VDDO1.8 + VDDIO, all outputs at 100MHz 36 45 mA 1
I
DDRPD
VDDR, CKPWRGD_PD# = 0 0.4 1 mA 1, 2
I
DDDIGPD
VDDDIG, CKPWRGD_PD# = 0 0.6 1.5 mA 1, 2
I
DDOPD
VDDO1.8 + VDDIO, CKPWRGD_PD# = 0 0.0 0.1 mA 1, 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input clock stopped.
Operating Supply Current
Powerdown Current
MARCH 14, 2017 9 9-OUTPUT 1.8V HCSL FANOUT BUFFER
9DBV0931 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle Distortion t
DCD
Measured differentially at 100MHz -1 -0.4 0.5 % 1,3
Skew, Input to Output t
p
dBYP
V
T
= 50% 1800 2378 3000 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 41 60 ps 1,4
Jitter, Cycle to Cycle t
jcyc-cyc
Additive Jitter 0.1 5 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform.
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock.
4
All outputs at default slew rate.
TA = T
COM
or T
IND
; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 0.1 5 N/A ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.4 N/A
ps
(rms)
1,2,3,4,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.01 0.4 N/A
ps
(rms)
1,2,3,4
t
jphPCIeG3
PCIe Gen 3
(2-4MHz or 2-5MHz, CDR = 10MHz)
0.00 0.1 N/A
ps
(rms)
1,2,3,4
t
jphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165 200 N/A
fs
(rms)
1,6
t
jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251 300 N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2].
5
Driven by 9FGV0831 or equivalent.
6
Rohde & Schwarz SMA100.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
Additive Phase Jitter
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

9DBV0931AKLF

Mfr. #:
Buy 9DBV0931AKLF
Manufacturer:
IDT
Description:
Clock Buffer 9-output 1.8 V PCIe Gen1-2-3 Fanout Buff
Lifecycle:
New from this manufacturer.
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